Bulk-layout-compatible 0.18-μm SOI-CMOS technology using body-tied partial-trench-isolation (PTI)

Yuuichi Hirano, Shigenobu Maeda, Takuji Matsumoto, Koji Nii, Toshiaki Iwamatsu, Yasuo Yamaguchi, Takashi Ipposhi, Hiroshi Kawashima, Shigeto Maegawa, Masahide Inuishi, Tadashi Nishimura

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

Partial-trench-isolated (PTI) 0.18-μm SOI-CMOS technology has been established to realize the body-tied structure and eliminate floating-body effects. The body potential of PTI SOI MOSFETs is fixed through the silicon layer under the PTI oxide. It was revealed that the body-tied PTI structure provides immunity from kink effects and improves drive current as compared with floating transistors. The SOI inherent merits were investigated by delay-time measurement. Low junction capacitance, coupling effects and low back-gate-bias effects of PTI CMOS offer excellent speed performance. Stable function and body-coupling benefits are obtained with proper body engineering. The full-bit functions of a 4-Mbit SRAM was obtained with a reasonable yield. The yield of the SOI SRAM is almost the same as that of the bulk SRAM. An abnormal leakage current was not observed up to a supply voltage of 2.6 V corresponding to the stress voltage of the burn-in process. It was demonstrated that PTI technology possesses layout and process compatibility with bulk. It is concluded that the PTI technology can expand SOI applications in system-level large-scale integrations (LSIs) by cutting off the floating-SOI constraint.

Original languageEnglish
Pages (from-to)2816-2822
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume48
Issue number12
DOIs
Publication statusPublished - 2001 Dec 1
Externally publishedYes

Keywords

  • High-speed integrated circuit
  • Isolation technology
  • SOI technology
  • SRAM
  • Simulation

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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  • Cite this

    Hirano, Y., Maeda, S., Matsumoto, T., Nii, K., Iwamatsu, T., Yamaguchi, Y., Ipposhi, T., Kawashima, H., Maegawa, S., Inuishi, M., & Nishimura, T. (2001). Bulk-layout-compatible 0.18-μm SOI-CMOS technology using body-tied partial-trench-isolation (PTI). IEEE Transactions on Electron Devices, 48(12), 2816-2822. https://doi.org/10.1109/16.974709