Bulk-layout-compatible 0.18-μm SOI-CMOS technology using body-tied partial-trench-isolation (PTI)

Yuuichi Hirano, Shigenobu Maeda, Takuji Matsumoto, Koji Nii, Toshiaki Iwamatsu, Yasuo Yamaguchi, Takashi Ipposhi, Hiroshi Kawashima, Shigeto Maegawa, Masahide Inuishi, Tadashi Nishimura

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

Partial-trench-isolated (PTI) 0.18-μm SOI-CMOS technology has been established to realize the body-tied structure and eliminate floating-body effects. The body potential of PTI SOI MOSFETs is fixed through the silicon layer under the PTI oxide. It was revealed that the body-tied PTI structure provides immunity from kink effects and improves drive current as compared with floating transistors. The SOI inherent merits were investigated by delay-time measurement. Low junction capacitance, coupling effects and low back-gate-bias effects of PTI CMOS offer excellent speed performance. Stable function and body-coupling benefits are obtained with proper body engineering. The full-bit functions of a 4-Mbit SRAM was obtained with a reasonable yield. The yield of the SOI SRAM is almost the same as that of the bulk SRAM. An abnormal leakage current was not observed up to a supply voltage of 2.6 V corresponding to the stress voltage of the burn-in process. It was demonstrated that PTI technology possesses layout and process compatibility with bulk. It is concluded that the PTI technology can expand SOI applications in system-level large-scale integrations (LSIs) by cutting off the floating-SOI constraint.

Original languageEnglish
Pages (from-to)2816-2822
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume48
Issue number12
DOIs
Publication statusPublished - 2001 Dec
Externally publishedYes

Fingerprint

Static random access storage
SOI (semiconductors)
layouts
isolation
CMOS
floating
LSI circuits
Electric potential
Silicon
Time measurement
Leakage currents
Oxides
Transistors
Capacitance
burn-in
large scale integration
immunity
electric potential
compatibility
leakage

Keywords

  • High-speed integrated circuit
  • Isolation technology
  • Simulation
  • SOI technology
  • SRAM

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Physics and Astronomy (miscellaneous)

Cite this

Hirano, Y., Maeda, S., Matsumoto, T., Nii, K., Iwamatsu, T., Yamaguchi, Y., ... Nishimura, T. (2001). Bulk-layout-compatible 0.18-μm SOI-CMOS technology using body-tied partial-trench-isolation (PTI). IEEE Transactions on Electron Devices, 48(12), 2816-2822. https://doi.org/10.1109/16.974709

Bulk-layout-compatible 0.18-μm SOI-CMOS technology using body-tied partial-trench-isolation (PTI). / Hirano, Yuuichi; Maeda, Shigenobu; Matsumoto, Takuji; Nii, Koji; Iwamatsu, Toshiaki; Yamaguchi, Yasuo; Ipposhi, Takashi; Kawashima, Hiroshi; Maegawa, Shigeto; Inuishi, Masahide; Nishimura, Tadashi.

In: IEEE Transactions on Electron Devices, Vol. 48, No. 12, 12.2001, p. 2816-2822.

Research output: Contribution to journalArticle

Hirano, Y, Maeda, S, Matsumoto, T, Nii, K, Iwamatsu, T, Yamaguchi, Y, Ipposhi, T, Kawashima, H, Maegawa, S, Inuishi, M & Nishimura, T 2001, 'Bulk-layout-compatible 0.18-μm SOI-CMOS technology using body-tied partial-trench-isolation (PTI)', IEEE Transactions on Electron Devices, vol. 48, no. 12, pp. 2816-2822. https://doi.org/10.1109/16.974709
Hirano, Yuuichi ; Maeda, Shigenobu ; Matsumoto, Takuji ; Nii, Koji ; Iwamatsu, Toshiaki ; Yamaguchi, Yasuo ; Ipposhi, Takashi ; Kawashima, Hiroshi ; Maegawa, Shigeto ; Inuishi, Masahide ; Nishimura, Tadashi. / Bulk-layout-compatible 0.18-μm SOI-CMOS technology using body-tied partial-trench-isolation (PTI). In: IEEE Transactions on Electron Devices. 2001 ; Vol. 48, No. 12. pp. 2816-2822.
@article{dbff77565a584e6aa14c65eb359e8d73,
title = "Bulk-layout-compatible 0.18-μm SOI-CMOS technology using body-tied partial-trench-isolation (PTI)",
abstract = "Partial-trench-isolated (PTI) 0.18-μm SOI-CMOS technology has been established to realize the body-tied structure and eliminate floating-body effects. The body potential of PTI SOI MOSFETs is fixed through the silicon layer under the PTI oxide. It was revealed that the body-tied PTI structure provides immunity from kink effects and improves drive current as compared with floating transistors. The SOI inherent merits were investigated by delay-time measurement. Low junction capacitance, coupling effects and low back-gate-bias effects of PTI CMOS offer excellent speed performance. Stable function and body-coupling benefits are obtained with proper body engineering. The full-bit functions of a 4-Mbit SRAM was obtained with a reasonable yield. The yield of the SOI SRAM is almost the same as that of the bulk SRAM. An abnormal leakage current was not observed up to a supply voltage of 2.6 V corresponding to the stress voltage of the burn-in process. It was demonstrated that PTI technology possesses layout and process compatibility with bulk. It is concluded that the PTI technology can expand SOI applications in system-level large-scale integrations (LSIs) by cutting off the floating-SOI constraint.",
keywords = "High-speed integrated circuit, Isolation technology, Simulation, SOI technology, SRAM",
author = "Yuuichi Hirano and Shigenobu Maeda and Takuji Matsumoto and Koji Nii and Toshiaki Iwamatsu and Yasuo Yamaguchi and Takashi Ipposhi and Hiroshi Kawashima and Shigeto Maegawa and Masahide Inuishi and Tadashi Nishimura",
year = "2001",
month = "12",
doi = "10.1109/16.974709",
language = "English",
volume = "48",
pages = "2816--2822",
journal = "IEEE Transactions on Electron Devices",
issn = "0018-9383",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "12",

}

TY - JOUR

T1 - Bulk-layout-compatible 0.18-μm SOI-CMOS technology using body-tied partial-trench-isolation (PTI)

AU - Hirano, Yuuichi

AU - Maeda, Shigenobu

AU - Matsumoto, Takuji

AU - Nii, Koji

AU - Iwamatsu, Toshiaki

AU - Yamaguchi, Yasuo

AU - Ipposhi, Takashi

AU - Kawashima, Hiroshi

AU - Maegawa, Shigeto

AU - Inuishi, Masahide

AU - Nishimura, Tadashi

PY - 2001/12

Y1 - 2001/12

N2 - Partial-trench-isolated (PTI) 0.18-μm SOI-CMOS technology has been established to realize the body-tied structure and eliminate floating-body effects. The body potential of PTI SOI MOSFETs is fixed through the silicon layer under the PTI oxide. It was revealed that the body-tied PTI structure provides immunity from kink effects and improves drive current as compared with floating transistors. The SOI inherent merits were investigated by delay-time measurement. Low junction capacitance, coupling effects and low back-gate-bias effects of PTI CMOS offer excellent speed performance. Stable function and body-coupling benefits are obtained with proper body engineering. The full-bit functions of a 4-Mbit SRAM was obtained with a reasonable yield. The yield of the SOI SRAM is almost the same as that of the bulk SRAM. An abnormal leakage current was not observed up to a supply voltage of 2.6 V corresponding to the stress voltage of the burn-in process. It was demonstrated that PTI technology possesses layout and process compatibility with bulk. It is concluded that the PTI technology can expand SOI applications in system-level large-scale integrations (LSIs) by cutting off the floating-SOI constraint.

AB - Partial-trench-isolated (PTI) 0.18-μm SOI-CMOS technology has been established to realize the body-tied structure and eliminate floating-body effects. The body potential of PTI SOI MOSFETs is fixed through the silicon layer under the PTI oxide. It was revealed that the body-tied PTI structure provides immunity from kink effects and improves drive current as compared with floating transistors. The SOI inherent merits were investigated by delay-time measurement. Low junction capacitance, coupling effects and low back-gate-bias effects of PTI CMOS offer excellent speed performance. Stable function and body-coupling benefits are obtained with proper body engineering. The full-bit functions of a 4-Mbit SRAM was obtained with a reasonable yield. The yield of the SOI SRAM is almost the same as that of the bulk SRAM. An abnormal leakage current was not observed up to a supply voltage of 2.6 V corresponding to the stress voltage of the burn-in process. It was demonstrated that PTI technology possesses layout and process compatibility with bulk. It is concluded that the PTI technology can expand SOI applications in system-level large-scale integrations (LSIs) by cutting off the floating-SOI constraint.

KW - High-speed integrated circuit

KW - Isolation technology

KW - Simulation

KW - SOI technology

KW - SRAM

UR - http://www.scopus.com/inward/record.url?scp=0035694263&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0035694263&partnerID=8YFLogxK

U2 - 10.1109/16.974709

DO - 10.1109/16.974709

M3 - Article

VL - 48

SP - 2816

EP - 2822

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

IS - 12

ER -