Bus via reduction based on floorplan revising

Ou He*, Sheqin Dong, Jinian Bian, Sotoshi Goto, Chung Kuan Cheng

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    5 Citations (Scopus)


    As a global interconnection, bus is critical for chip performance in deep submicron technology. Reducing bus routing vias will facilitate the lithography and give bus routing a higher yield and also a higher performance. In this paper, we present a floorplan revising method to minimize the number of reducible routing vias with a controllable loss on the chip area and wirelength. Therefore, it is easy to make a proper tradeoff between via reduction and revising loss. Experiments show that our method reaches a 96.2% and 93.5% reduction of routing vias, which is close to 100% and runs fast. Besides, our revising is friendly to all third-party floorplanners, which can be applied to any existing floorplans to reduce vias. It is also scalable to larger benchmarks.

    Original languageEnglish
    Title of host publicationProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
    Number of pages6
    Publication statusPublished - 2010
    Event20th Great Lakes Symposium on VLSI, GLSVLSI 2010 - Providence, RI
    Duration: 2010 May 162010 May 18


    Other20th Great Lakes Symposium on VLSI, GLSVLSI 2010
    CityProvidence, RI


    • bus routing
    • floorplan revising
    • via reduction

    ASJC Scopus subject areas

    • Engineering(all)


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