TY - GEN
T1 - BusMesh NoC
T2 - 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
AU - Lee, Seung Ju
AU - Yanagisawa, Masao
AU - Ohtsuki, Tatsuo
AU - Togawa, Nozomu
PY - 2010/12/1
Y1 - 2010/12/1
N2 - Network-on-chip (NoC) architectures are emerged as a promising solution to the lack of scalability in multi-processor systems-on-chips (MPSoCs). In this paper, A busmesh network-on-chip (BMNoC) architecture is proposed, together with simulation results. It is comprised of bus-based connection and global mesh routers to enhance the performance of on-chip communication. Furthermore, MPEG-4, H.264 and a hybrid application mixed MPEG-4 and H.264 on our architecture illustrates the better performance than earlier studies and feasibility of BMNoC.
AB - Network-on-chip (NoC) architectures are emerged as a promising solution to the lack of scalability in multi-processor systems-on-chips (MPSoCs). In this paper, A busmesh network-on-chip (BMNoC) architecture is proposed, together with simulation results. It is comprised of bus-based connection and global mesh routers to enhance the performance of on-chip communication. Furthermore, MPEG-4, H.264 and a hybrid application mixed MPEG-4 and H.264 on our architecture illustrates the better performance than earlier studies and feasibility of BMNoC.
KW - A novel NoC architecture
KW - BusMesh NoC (BMNoC)
KW - Network-on-Chip (NoC)
UR - http://www.scopus.com/inward/record.url?scp=79959244733&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79959244733&partnerID=8YFLogxK
U2 - 10.1109/APCCAS.2010.5774825
DO - 10.1109/APCCAS.2010.5774825
M3 - Conference contribution
AN - SCOPUS:79959244733
SN - 9781424474561
T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
SP - 712
EP - 715
BT - Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
Y2 - 6 December 2010 through 9 December 2010
ER -