BusMesh NoC: A novel NoC architecture comprised of bus-based connection and global mesh routers

Seung Ju Lee, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

Network-on-chip (NoC) architectures are emerged as a promising solution to the lack of scalability in multi-processor systems-on-chips (MPSoCs). In this paper, A busmesh network-on-chip (BMNoC) architecture is proposed, together with simulation results. It is comprised of bus-based connection and global mesh routers to enhance the performance of on-chip communication. Furthermore, MPEG-4, H.264 and a hybrid application mixed MPEG-4 and H.264 on our architecture illustrates the better performance than earlier studies and feasibility of BMNoC.

Original languageEnglish
Title of host publicationProceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
Pages712-715
Number of pages4
DOIs
Publication statusPublished - 2010 Dec 1
Event2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 - Kuala Lumpur, Malaysia
Duration: 2010 Dec 62010 Dec 9

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

Conference2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
CountryMalaysia
CityKuala Lumpur
Period10/12/610/12/9

Keywords

  • A novel NoC architecture
  • BusMesh NoC (BMNoC)
  • Network-on-Chip (NoC)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Lee, S. J., Yanagisawa, M., Ohtsuki, T., & Togawa, N. (2010). BusMesh NoC: A novel NoC architecture comprised of bus-based connection and global mesh routers. In Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 (pp. 712-715). [5774825] (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2010.5774825