Cache miss reduction through hardware-assisted loop optimization

Kang Zhao, Jinian Bian, Chenqian Jiang, Sheqin Dong, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

To reduce the miss rate of the instruction cache, a hardware-assisted loop optimization method is proposed in this paper. This method utilizes the hardware/software co-design strategy on the behavior level. Especially, this method is equipped with the specific instruction set to limit the cache misses, which can be viewed as a set of hardware for special purposes. Then based on the specific instruction set, a scheduling process is integrated which reduces the cache miss rate through the code transformation. Finally, a set of benchmarks from MediaBench1.0 are tested on the SimpleScalar platform to assist the proposed method. The final experiments indicate that 26% enhancement can be obtained for the cache miss reduction, where the specific instruction generation and the scheduling processes contribute about 23% and 3% respectively.

Original languageEnglish
Title of host publicationProceedings of the 2008 12th International Conference on Computer Supported Cooperative Work in Design, CSCWD
Pages129-134
Number of pages6
Volume1
DOIs
Publication statusPublished - 2008
Event2008 12th International Conference on Computer Supported Cooperative Work in Design, CSCWD - Xi'an
Duration: 2008 Apr 162008 Apr 18

Other

Other2008 12th International Conference on Computer Supported Cooperative Work in Design, CSCWD
CityXi'an
Period08/4/1608/4/18

Fingerprint

Hardware
Scheduling
Experiments

Keywords

  • ASIP
  • Cache miss
  • CSCW design
  • Hardware/software co-design

ASJC Scopus subject areas

  • Artificial Intelligence
  • Computer Networks and Communications
  • Human-Computer Interaction

Cite this

Zhao, K., Bian, J., Jiang, C., Dong, S., & Goto, S. (2008). Cache miss reduction through hardware-assisted loop optimization. In Proceedings of the 2008 12th International Conference on Computer Supported Cooperative Work in Design, CSCWD (Vol. 1, pp. 129-134). [4536969] https://doi.org/10.1109/CSCWD.2008.4536969

Cache miss reduction through hardware-assisted loop optimization. / Zhao, Kang; Bian, Jinian; Jiang, Chenqian; Dong, Sheqin; Goto, Satoshi.

Proceedings of the 2008 12th International Conference on Computer Supported Cooperative Work in Design, CSCWD. Vol. 1 2008. p. 129-134 4536969.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zhao, K, Bian, J, Jiang, C, Dong, S & Goto, S 2008, Cache miss reduction through hardware-assisted loop optimization. in Proceedings of the 2008 12th International Conference on Computer Supported Cooperative Work in Design, CSCWD. vol. 1, 4536969, pp. 129-134, 2008 12th International Conference on Computer Supported Cooperative Work in Design, CSCWD, Xi'an, 08/4/16. https://doi.org/10.1109/CSCWD.2008.4536969
Zhao K, Bian J, Jiang C, Dong S, Goto S. Cache miss reduction through hardware-assisted loop optimization. In Proceedings of the 2008 12th International Conference on Computer Supported Cooperative Work in Design, CSCWD. Vol. 1. 2008. p. 129-134. 4536969 https://doi.org/10.1109/CSCWD.2008.4536969
Zhao, Kang ; Bian, Jinian ; Jiang, Chenqian ; Dong, Sheqin ; Goto, Satoshi. / Cache miss reduction through hardware-assisted loop optimization. Proceedings of the 2008 12th International Conference on Computer Supported Cooperative Work in Design, CSCWD. Vol. 1 2008. pp. 129-134
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