Calculating the effective capacitance for interconnect loads based on thevenin model

Shuai Fang, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    Interconnect wires give large influences on circuit delay in very deep submicron designs. Thevenin model and effective capacitance Ceff concept are usually used to calculate the delay of gate with interconnect loads. In the researches before, the condition that the charges transferred to C eff and RC -π are not equal was not considered. With the progress of IC process technology, its influence on Static Timing Analysis becomes larger. In this paper, we consider this condition, and propose an new algorithm for calculating the effective capacitance based on Thevenin model. Experimental results show that it is in agreement with the Spice simulation.

    Original languageEnglish
    Title of host publication2006 International Conference on Communications, Circuits and Systems, ICCCAS, Proceedings
    Pages2474-2477
    Number of pages4
    Volume4
    DOIs
    Publication statusPublished - 2006
    Event2006 International Conference on Communications, Circuits and Systems, ICCCAS - Guilin
    Duration: 2006 Jun 252006 Jun 28

    Other

    Other2006 International Conference on Communications, Circuits and Systems, ICCCAS
    CityGuilin
    Period06/6/2506/6/28

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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  • Cite this

    Fang, S., Huang, Z., Kurokawa, A., & Inoue, Y. (2006). Calculating the effective capacitance for interconnect loads based on thevenin model. In 2006 International Conference on Communications, Circuits and Systems, ICCCAS, Proceedings (Vol. 4, pp. 2474-2477). [4064423] https://doi.org/10.1109/ICCCAS.2006.285176