Capacitance and yield evaluations using a 90-nm process technology based on the dense power-ground interconnect architecture

Atsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    In the VLSI design of sub-100-nm technologies, most engineers in the process, chip-design, and EDA areas are acutely aware of a tough red brick wall emerging because of process variability and physical integrity issues. Process variability is not only a fabrication problem, but also a serious design issue. Similarly, physical integrity problems are not only design and EDA issues, but also process-related architecture problems. In this paper, we investigate the practicality of a dense power-ground interconnect architecture developed to ensure physical design integrity. The interconnect architecture basically consists of adjoining power and ground lines. We describe the design methodologies and a simple method for calculating the decoupling capacitance (decap) values, and report both calculated and measured decap values for the architecture. We also report measurement results regarding the signal line capacitance and the interconnect defect-type yield of a 90-nm process technology.

    Original languageEnglish
    Title of host publicationProceedings - International Symposium on Quality Electronic Design, ISQED
    Pages153-158
    Number of pages6
    DOIs
    Publication statusPublished - 2005
    Event6th International Symposium on Quality Electronic Design, ISQED 2005 - San Jose, CA
    Duration: 2005 Mar 212005 Mar 23

    Other

    Other6th International Symposium on Quality Electronic Design, ISQED 2005
    CitySan Jose, CA
    Period05/3/2105/3/23

    Fingerprint

    Capacitance
    Brick
    Engineers
    Fabrication
    Defects

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering
    • Safety, Risk, Reliability and Quality

    Cite this

    Kurokawa, A., Yamamoto, M., Ono, N., Kage, T., Inoue, Y., & Masuda, H. (2005). Capacitance and yield evaluations using a 90-nm process technology based on the dense power-ground interconnect architecture. In Proceedings - International Symposium on Quality Electronic Design, ISQED (pp. 153-158). [1410575] https://doi.org/10.1109/ISQED.2005.29

    Capacitance and yield evaluations using a 90-nm process technology based on the dense power-ground interconnect architecture. / Kurokawa, Atsushi; Yamamoto, Masaharu; Ono, Nobuto; Kage, Tetsuro; Inoue, Yasuaki; Masuda, Hiroo.

    Proceedings - International Symposium on Quality Electronic Design, ISQED. 2005. p. 153-158 1410575.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Kurokawa, A, Yamamoto, M, Ono, N, Kage, T, Inoue, Y & Masuda, H 2005, Capacitance and yield evaluations using a 90-nm process technology based on the dense power-ground interconnect architecture. in Proceedings - International Symposium on Quality Electronic Design, ISQED., 1410575, pp. 153-158, 6th International Symposium on Quality Electronic Design, ISQED 2005, San Jose, CA, 05/3/21. https://doi.org/10.1109/ISQED.2005.29
    Kurokawa A, Yamamoto M, Ono N, Kage T, Inoue Y, Masuda H. Capacitance and yield evaluations using a 90-nm process technology based on the dense power-ground interconnect architecture. In Proceedings - International Symposium on Quality Electronic Design, ISQED. 2005. p. 153-158. 1410575 https://doi.org/10.1109/ISQED.2005.29
    Kurokawa, Atsushi ; Yamamoto, Masaharu ; Ono, Nobuto ; Kage, Tetsuro ; Inoue, Yasuaki ; Masuda, Hiroo. / Capacitance and yield evaluations using a 90-nm process technology based on the dense power-ground interconnect architecture. Proceedings - International Symposium on Quality Electronic Design, ISQED. 2005. pp. 153-158
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