Cascaded DMA controller for speedup of indirect memory access in irregular applications

Tomoya Kashimata, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Indirect memory accesses caused by sparse linear algebra calculations are widely used in important real applications. However, they also cause serious inefficient memory accesses and pipeline stalls resulting low execution efficiency even with high memory bandwidth and much computational resource. One of the important issues of indirect memory accesses, such as accessing A[B[i]], is it requires two succeeding different memory accesses: the index loads (B[i]) and the following data element accesses (A[B[i]]). To overcome this situation, we propose the Cascaded-DMAC (CDMAC). This CDMAC is intended to be attached in each core of a multicore chip in addition to a CPU core, a vector accelerator, and a local data memory. It performs data transfers between an off-chip main memory and an in-core local data memory, which provides data to the accelerator. The key idea of the CDMAC is cascading two DMACs so that the first one loads indices, then the second one accesses data elements by using these indices. Thus, this organization realizes the autonomous indirect memory accesses by giving an index array and an element array, and obtains the efficient SIMD computations by lining up the sparse data into the local data memory. We implemented a multicore processor having the proposed CDMAC on an FPGA board. The evaluation result of sparse matrix-vector multiplications on the FPGA shows that the CDMAC achieves 17x speedup at most compared with the CPU data transfer.

Original languageEnglish
Title of host publication2019 IEEE/ACM 9th Workshop on Irregular Applications
Subtitle of host publicationArchitectures and Algorithms, IA3 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages71-76
Number of pages6
ISBN (Electronic)9781728159874
DOIs
Publication statusPublished - 2019 Nov
Event9th IEEE/ACM Workshop on Irregular Applications: Architectures and Algorithms, IA3 2019 - Denver, United States
Duration: 2019 Nov 18 → …

Publication series

Name2019 IEEE/ACM 9th Workshop on Irregular Applications: Architectures and Algorithms, IA3 2019

Conference

Conference9th IEEE/ACM Workshop on Irregular Applications: Architectures and Algorithms, IA3 2019
CountryUnited States
CityDenver
Period19/11/18 → …

Keywords

  • Cascaded DMA Controller
  • CDMAC
  • DMA
  • DMAC
  • Indirect memory access
  • SMVM
  • Sparse matrix vector multiplication
  • SpMV

ASJC Scopus subject areas

  • Software
  • Computational Mathematics
  • Hardware and Architecture

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  • Cite this

    Kashimata, T., Kitamura, T., Kimura, K., & Kasahara, H. (2019). Cascaded DMA controller for speedup of indirect memory access in irregular applications. In 2019 IEEE/ACM 9th Workshop on Irregular Applications: Architectures and Algorithms, IA3 2019 (pp. 71-76). [8945078] (2019 IEEE/ACM 9th Workshop on Irregular Applications: Architectures and Algorithms, IA3 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IA349570.2019.00017