Cell array design with row-driven source line in block shunt architecture applicable to future 6f2 1t1mtj memory

Tongshuang Huang, Takashi Ohsawa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we propose a new 1T1MTJ cell array architecture with SL parallel to WL to achieve a small cell size, in which page mode write can be realized without performance degradation. We propose a row-driven source line (RSL) 1T1MTJ memory cell array architecture for minimizing the cell size and a corresponding operational waveform. A block shunt architecture (BSA) that shunts lower source line (LSL) and upper source line (USL) is proposed to make page mode write possible. Size of 1T1MTJ cell can be shrunk to 6F2 when the state-of-The-Art design rules are applied.

Original languageEnglish
Title of host publication2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728109428
DOIs
Publication statusPublished - 2019 Apr 1
Event2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019 - Hsinchu, Taiwan, Province of China
Duration: 2019 Apr 222019 Apr 25

Publication series

Name2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019

Conference

Conference2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019
CountryTaiwan, Province of China
CityHsinchu
Period19/4/2219/4/25

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Huang, T., & Ohsawa, T. (2019). Cell array design with row-driven source line in block shunt architecture applicable to future 6f2 1t1mtj memory. In 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019 [8804671] (2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-TSA.2019.8804671