CIRCUIT DESIGN OF DYNAMIC MOS RAM WITH CONSIDERATION OF SOFT ERROR.

Yasuji Nagayama, Masaki Kumanoya, Michihiro Yamada, Tsutomu Yoshihara, Makoto Taniguchi

Research output: Contribution to journalArticle

Abstract

Dynamic MOS RAMs (MOS (D) RAMs) have been developed according to scaling relationships. But it is necessary to correct the scaling relationships because of soft error. In this paper, a modified scaling law is described based on the assumption that the soft error becomes the governing condition of the scaling law. In addition, a new device structure and circuit configuration are proposed to realize high-speed, low soft error rate and low power consumption.

Original languageEnglish
Pages (from-to)92-101
Number of pages10
JournalElectronics & communications in Japan
Volume65
Issue number7
Publication statusPublished - 1983 Jul
Externally publishedYes

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Nagayama, Y., Kumanoya, M., Yamada, M., Yoshihara, T., & Taniguchi, M. (1983). CIRCUIT DESIGN OF DYNAMIC MOS RAM WITH CONSIDERATION OF SOFT ERROR. Electronics & communications in Japan, 65(7), 92-101.