Circuit design of dynamic MOS RAM with consideration of soft error

Yasuji Nagayama, Masaki Kumanoya, Michihiro Yamada, Tsutomu Yoshihara, Makoto Taniguchi

Research output: Contribution to journalArticle

Abstract

Dynamic MOS RAMs (MOS (D) RAMs) have been developed according to scaling relationships. But it is necessary to correct the scaling relationships because of soft error. In this paper, a modified scaling law is described based on the assumption that the soft error becomes the governing condition of the scaling law. In addition, a new device structure and circuit configuration are proposed to realize high‐speed, low soft error rate and low power consumption. As a result of applying it to a 5‐V 16‐K MOS (D) RAM, a performance index of 0.6 pJ/bit and soft error rate of 4 × 107 device. hours are obtained. The adequacy of the modified scaling law is examined by considering a 12‐V 16‐K MOS (D) RAM with scaling constant k = 1 and a 5‐V 16‐K MOS (D) RAM with k = 2. It is shown that circuit design with consideration of soft error cannot achieve large improvement of the performance index of high‐capacity MOS (D) RAM and that the soft error is an impediment to high‐performance MOS (D) RAM.

Original languageEnglish
Pages (from-to)92-101
Number of pages10
JournalElectronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi)
Volume65
Issue number7
DOIs
Publication statusPublished - 1982
Externally publishedYes

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Random access storage
Networks (circuits)
Scaling laws
Electric power utilization

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

Circuit design of dynamic MOS RAM with consideration of soft error. / Nagayama, Yasuji; Kumanoya, Masaki; Yamada, Michihiro; Yoshihara, Tsutomu; Taniguchi, Makoto.

In: Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi), Vol. 65, No. 7, 1982, p. 92-101.

Research output: Contribution to journalArticle

Nagayama, Yasuji ; Kumanoya, Masaki ; Yamada, Michihiro ; Yoshihara, Tsutomu ; Taniguchi, Makoto. / Circuit design of dynamic MOS RAM with consideration of soft error. In: Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi). 1982 ; Vol. 65, No. 7. pp. 92-101.
@article{dc6c72ddae6f48e483befd8210e7c25f,
title = "Circuit design of dynamic MOS RAM with consideration of soft error",
abstract = "Dynamic MOS RAMs (MOS (D) RAMs) have been developed according to scaling relationships. But it is necessary to correct the scaling relationships because of soft error. In this paper, a modified scaling law is described based on the assumption that the soft error becomes the governing condition of the scaling law. In addition, a new device structure and circuit configuration are proposed to realize high‐speed, low soft error rate and low power consumption. As a result of applying it to a 5‐V 16‐K MOS (D) RAM, a performance index of 0.6 pJ/bit and soft error rate of 4 × 107 device. hours are obtained. The adequacy of the modified scaling law is examined by considering a 12‐V 16‐K MOS (D) RAM with scaling constant k = 1 and a 5‐V 16‐K MOS (D) RAM with k = 2. It is shown that circuit design with consideration of soft error cannot achieve large improvement of the performance index of high‐capacity MOS (D) RAM and that the soft error is an impediment to high‐performance MOS (D) RAM.",
author = "Yasuji Nagayama and Masaki Kumanoya and Michihiro Yamada and Tsutomu Yoshihara and Makoto Taniguchi",
year = "1982",
doi = "10.1002/ecja.4410650712",
language = "English",
volume = "65",
pages = "92--101",
journal = "Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi)",
issn = "8756-6621",
publisher = "John Wiley and Sons Inc.",
number = "7",

}

TY - JOUR

T1 - Circuit design of dynamic MOS RAM with consideration of soft error

AU - Nagayama, Yasuji

AU - Kumanoya, Masaki

AU - Yamada, Michihiro

AU - Yoshihara, Tsutomu

AU - Taniguchi, Makoto

PY - 1982

Y1 - 1982

N2 - Dynamic MOS RAMs (MOS (D) RAMs) have been developed according to scaling relationships. But it is necessary to correct the scaling relationships because of soft error. In this paper, a modified scaling law is described based on the assumption that the soft error becomes the governing condition of the scaling law. In addition, a new device structure and circuit configuration are proposed to realize high‐speed, low soft error rate and low power consumption. As a result of applying it to a 5‐V 16‐K MOS (D) RAM, a performance index of 0.6 pJ/bit and soft error rate of 4 × 107 device. hours are obtained. The adequacy of the modified scaling law is examined by considering a 12‐V 16‐K MOS (D) RAM with scaling constant k = 1 and a 5‐V 16‐K MOS (D) RAM with k = 2. It is shown that circuit design with consideration of soft error cannot achieve large improvement of the performance index of high‐capacity MOS (D) RAM and that the soft error is an impediment to high‐performance MOS (D) RAM.

AB - Dynamic MOS RAMs (MOS (D) RAMs) have been developed according to scaling relationships. But it is necessary to correct the scaling relationships because of soft error. In this paper, a modified scaling law is described based on the assumption that the soft error becomes the governing condition of the scaling law. In addition, a new device structure and circuit configuration are proposed to realize high‐speed, low soft error rate and low power consumption. As a result of applying it to a 5‐V 16‐K MOS (D) RAM, a performance index of 0.6 pJ/bit and soft error rate of 4 × 107 device. hours are obtained. The adequacy of the modified scaling law is examined by considering a 12‐V 16‐K MOS (D) RAM with scaling constant k = 1 and a 5‐V 16‐K MOS (D) RAM with k = 2. It is shown that circuit design with consideration of soft error cannot achieve large improvement of the performance index of high‐capacity MOS (D) RAM and that the soft error is an impediment to high‐performance MOS (D) RAM.

UR - http://www.scopus.com/inward/record.url?scp=84984311047&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84984311047&partnerID=8YFLogxK

U2 - 10.1002/ecja.4410650712

DO - 10.1002/ecja.4410650712

M3 - Article

AN - SCOPUS:84984311047

VL - 65

SP - 92

EP - 101

JO - Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi)

JF - Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi)

SN - 8756-6621

IS - 7

ER -