### Abstract

An initial circuit is partitioned into multi-field programmable gate arrays (FPGA) chips using an algorithm based on recursive bi-partitioning of a circuit. In each bipartitioning, the algorithm searches a partitioning position of a circuit such that each of the partitioned subcircuits is accommodated in each FPGA chip, making the number of signal nets between chips as small as possible. Experimental results show that it decreases the maximum number of I/O blocks per chip by a maximum of 49% compared with other conventional algorithms.

Original language | English |
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Pages (from-to) | 1765-1776 |

Number of pages | 12 |

Journal | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |

Volume | E78-A |

Issue number | 12 |

Publication status | Published - 1995 Dec |

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### ASJC Scopus subject areas

- Hardware and Architecture
- Information Systems
- Electrical and Electronic Engineering

### Cite this

*IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences*,

*E78-A*(12), 1765-1776.

**Circuit partitioning algorithm with replication capability for multi-FPGA systems.** / Togawa, Nozomu; Sato, Masao; Ohtsuki, Tatsuo.

Research output: Contribution to journal › Article

*IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences*, vol. E78-A, no. 12, pp. 1765-1776.

}

TY - JOUR

T1 - Circuit partitioning algorithm with replication capability for multi-FPGA systems

AU - Togawa, Nozomu

AU - Sato, Masao

AU - Ohtsuki, Tatsuo

PY - 1995/12

Y1 - 1995/12

N2 - An initial circuit is partitioned into multi-field programmable gate arrays (FPGA) chips using an algorithm based on recursive bi-partitioning of a circuit. In each bipartitioning, the algorithm searches a partitioning position of a circuit such that each of the partitioned subcircuits is accommodated in each FPGA chip, making the number of signal nets between chips as small as possible. Experimental results show that it decreases the maximum number of I/O blocks per chip by a maximum of 49% compared with other conventional algorithms.

AB - An initial circuit is partitioned into multi-field programmable gate arrays (FPGA) chips using an algorithm based on recursive bi-partitioning of a circuit. In each bipartitioning, the algorithm searches a partitioning position of a circuit such that each of the partitioned subcircuits is accommodated in each FPGA chip, making the number of signal nets between chips as small as possible. Experimental results show that it decreases the maximum number of I/O blocks per chip by a maximum of 49% compared with other conventional algorithms.

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UR - http://www.scopus.com/inward/citedby.url?scp=0029509891&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0029509891

VL - E78-A

SP - 1765

EP - 1776

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

SN - 0916-8508

IS - 12

ER -