Circuit partitioning algorithm with replication capability for multi-FPGA systems

Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki

    Research output: Contribution to journalArticle

    2 Citations (Scopus)

    Abstract

    An initial circuit is partitioned into multi-field programmable gate arrays (FPGA) chips using an algorithm based on recursive bi-partitioning of a circuit. In each bipartitioning, the algorithm searches a partitioning position of a circuit such that each of the partitioned subcircuits is accommodated in each FPGA chip, making the number of signal nets between chips as small as possible. Experimental results show that it decreases the maximum number of I/O blocks per chip by a maximum of 49% compared with other conventional algorithms.

    Original languageEnglish
    Pages (from-to)1765-1776
    Number of pages12
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE78-A
    Issue number12
    Publication statusPublished - 1995 Dec

    Fingerprint

    Field Programmable Gate Array
    Replication
    Field programmable gate arrays (FPGA)
    Partitioning
    Chip
    Networks (circuits)
    Search Algorithm
    Decrease
    Experimental Results

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Information Systems
    • Electrical and Electronic Engineering

    Cite this

    Circuit partitioning algorithm with replication capability for multi-FPGA systems. / Togawa, Nozomu; Sato, Masao; Ohtsuki, Tatsuo.

    In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E78-A, No. 12, 12.1995, p. 1765-1776.

    Research output: Contribution to journalArticle

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