An initial circuit is partitioned into multi-field programmable gate arrays (FPGA) chips using an algorithm based on recursive bi-partitioning of a circuit. In each bipartitioning, the algorithm searches a partitioning position of a circuit such that each of the partitioned subcircuits is accommodated in each FPGA chip, making the number of signal nets between chips as small as possible. Experimental results show that it decreases the maximum number of I/O blocks per chip by a maximum of 49% compared with other conventional algorithms.
|Number of pages||12|
|Journal||IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences|
|Publication status||Published - 1995 Dec|
ASJC Scopus subject areas
- Hardware and Architecture
- Information Systems
- Electrical and Electronic Engineering