Clock buffer placement algorithm for wire-delay-dominated timing model

M. Edahiro*, R. J. Lipton

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

4 Citations (Scopus)


A clock buffer placement algorithm is proposed for future technologies in which wire delay dominates signal delay. In such technologies, buffers need to be placed so as to minimize the maximum wire delay. We formulate the problem into a non-linear programming, and solve it by an iteration method with a randomized technique. We applied our buffer placement algorithm with a zero-skew router to several benchmark data, and show that our algorithm achieves 30% less delay time than a H-tree based algorithm.

Original languageEnglish
Pages (from-to)143-147
Number of pages5
JournalProceedings of the IEEE Great Lakes Symposium on VLSI
Publication statusPublished - 1996
Externally publishedYes
EventProceedings of the 1996 6th Great Lakes Symposium on VLSI, GLSVLSI - Ames, IA, USA
Duration: 1996 Mar 221996 Mar 23

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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