Clock buffer placement algorithm for wire-delay-dominated timing model

M. Edahiro; R. J. Lipton

Clock buffer placement algorithm for wire-delay-dominated timing model

M. Edahiro^*, R. J. Lipton

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

4 Citations (Scopus)

Abstract

A clock buffer placement algorithm is proposed for future technologies in which wire delay dominates signal delay. In such technologies, buffers need to be placed so as to minimize the maximum wire delay. We formulate the problem into a non-linear programming, and solve it by an iteration method with a randomized technique. We applied our buffer placement algorithm with a zero-skew router to several benchmark data, and show that our algorithm achieves 30% less delay time than a H-tree based algorithm.

Original language	English
Pages (from-to)	143-147
Number of pages	5
Journal	Proceedings of the IEEE Great Lakes Symposium on VLSI
Publication status	Published - 1996
Externally published	Yes
Event	Proceedings of the 1996 6th Great Lakes Symposium on VLSI, GLSVLSI - Ames, IA, USA Duration: 1996 Mar 22 → 1996 Mar 23

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "Clock buffer placement algorithm for wire-delay-dominated timing model",

abstract = "A clock buffer placement algorithm is proposed for future technologies in which wire delay dominates signal delay. In such technologies, buffers need to be placed so as to minimize the maximum wire delay. We formulate the problem into a non-linear programming, and solve it by an iteration method with a randomized technique. We applied our buffer placement algorithm with a zero-skew router to several benchmark data, and show that our algorithm achieves 30% less delay time than a H-tree based algorithm.",

author = "M. Edahiro and Lipton, {R. J.}",

year = "1996",

language = "English",

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journal = "Proceedings of the IEEE Great Lakes Symposium on VLSI",

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note = "Proceedings of the 1996 6th Great Lakes Symposium on VLSI, GLSVLSI ; Conference date: 22-03-1996 Through 23-03-1996",

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AU - Lipton, R. J.

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N2 - A clock buffer placement algorithm is proposed for future technologies in which wire delay dominates signal delay. In such technologies, buffers need to be placed so as to minimize the maximum wire delay. We formulate the problem into a non-linear programming, and solve it by an iteration method with a randomized technique. We applied our buffer placement algorithm with a zero-skew router to several benchmark data, and show that our algorithm achieves 30% less delay time than a H-tree based algorithm.

AB - A clock buffer placement algorithm is proposed for future technologies in which wire delay dominates signal delay. In such technologies, buffers need to be placed so as to minimize the maximum wire delay. We formulate the problem into a non-linear programming, and solve it by an iteration method with a randomized technique. We applied our buffer placement algorithm with a zero-skew router to several benchmark data, and show that our algorithm achieves 30% less delay time than a H-tree based algorithm.

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M3 - Conference article

AN - SCOPUS:0029708404

SN - 1066-1395

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JO - Proceedings of the IEEE Great Lakes Symposium on VLSI

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T2 - Proceedings of the 1996 6th Great Lakes Symposium on VLSI, GLSVLSI

Y2 - 22 March 1996 through 23 March 1996

ER -

Clock buffer placement algorithm for wire-delay-dominated timing model

Abstract

ASJC Scopus subject areas

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