Clock skew estimate modeling for FPGA high-level synthesis and its application

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)

    Abstract

    Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications. Clock network in FPGA has already been built before implementing any circuits, which may lead a large impact of clock skews and then degrade operation frequency. In this paper, we formulate a clock skew estimate model for FPGA-HLS (CSEF). CSEF is an accurate model to estimate clock skews in HLS flow. CSEF is then integrated into a floorplan-aware HLS algorithm targeting FPGA designs. Experimental results demonstrate that our HLS algorithm can realize FPGA designs which reduce the latency by up to 19% compared with conventional approaches.

    Original languageEnglish
    Title of host publicationProceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    ISBN (Electronic)9781479984831
    DOIs
    Publication statusPublished - 2016 Jul 19
    Event11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 - Chengdu, China
    Duration: 2015 Nov 32015 Nov 6

    Other

    Other11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
    CountryChina
    CityChengdu
    Period15/11/315/11/6

    Fingerprint

    Field programmable gate arrays (FPGA)
    Clocks
    High level synthesis
    Networks (circuits)

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

    Cite this

    Fujiwara, K., Kawamura, K., Yanagisawa, M., & Togawa, N. (2016). Clock skew estimate modeling for FPGA high-level synthesis and its application. In Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015 [7516905] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASICON.2015.7516905

    Clock skew estimate modeling for FPGA high-level synthesis and its application. / Fujiwara, Koichi; Kawamura, Kazushi; Yanagisawa, Masao; Togawa, Nozomu.

    Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 2016. 7516905.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Fujiwara, K, Kawamura, K, Yanagisawa, M & Togawa, N 2016, Clock skew estimate modeling for FPGA high-level synthesis and its application. in Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015., 7516905, Institute of Electrical and Electronics Engineers Inc., 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015, Chengdu, China, 15/11/3. https://doi.org/10.1109/ASICON.2015.7516905
    Fujiwara K, Kawamura K, Yanagisawa M, Togawa N. Clock skew estimate modeling for FPGA high-level synthesis and its application. In Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc. 2016. 7516905 https://doi.org/10.1109/ASICON.2015.7516905
    Fujiwara, Koichi ; Kawamura, Kazushi ; Yanagisawa, Masao ; Togawa, Nozomu. / Clock skew estimate modeling for FPGA high-level synthesis and its application. Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 2016.
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