Clocked CMOS adiabatic logic with low-power dissipation

He Li, Yimeng Zhang, Tsutomu Yoshihara

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    8 Citations (Scopus)

    Abstract

    This paper presents a new low-power adiabatic logic structure called Clocked CMOS Adiabatic Logic (CCAL), which is based on the Clocked CMOS logic. CCAL is powered by two complementary sinusoidal supply clocks. To demonstrate the energy efficiency of CCAL, eight-inverter chain is simulated to show the energy comparison among CCAL, Quasi-Static Energy Recovery Logic (QSERL) and conventional static CMOS with the Rohm 0.18 μm process. The simulation results indicate that CCAL implementation reduces about 40% energy at 200 MHz compared to the static CMOS. And below 100 MHz CCAL eight-inverter chain always has lower dissipation than the QSERL implementation.

    Original languageEnglish
    Title of host publicationISOCC 2013 - 2013 International SoC Design Conference
    PublisherIEEE Computer Society
    Pages64-67
    Number of pages4
    ISBN (Print)9781479911417
    DOIs
    Publication statusPublished - 2013
    Event2013 International SoC Design Conference, ISOCC 2013 - Busan
    Duration: 2013 Nov 172013 Nov 19

    Other

    Other2013 International SoC Design Conference, ISOCC 2013
    CityBusan
    Period13/11/1713/11/19

    Keywords

    • adiabatic logic
    • CCAL
    • Clocked CMOS
    • inverter chain
    • low power

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

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  • Cite this

    Li, H., Zhang, Y., & Yoshihara, T. (2013). Clocked CMOS adiabatic logic with low-power dissipation. In ISOCC 2013 - 2013 International SoC Design Conference (pp. 64-67). [6863986] IEEE Computer Society. https://doi.org/10.1109/ISOCC.2013.6863986