Clocked CMOS adiabatic logic with low-power dissipation

He Li; Yimeng Zhang; Tsutomu Yoshihara

doi:10.1109/ISOCC.2013.6863986

Clocked CMOS adiabatic logic with low-power dissipation

He Li, Yimeng Zhang, Tsutomu Yoshihara

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

13 Citations (Scopus)

Abstract

This paper presents a new low-power adiabatic logic structure called Clocked CMOS Adiabatic Logic (CCAL), which is based on the Clocked CMOS logic. CCAL is powered by two complementary sinusoidal supply clocks. To demonstrate the energy efficiency of CCAL, eight-inverter chain is simulated to show the energy comparison among CCAL, Quasi-Static Energy Recovery Logic (QSERL) and conventional static CMOS with the Rohm 0.18 μm process. The simulation results indicate that CCAL implementation reduces about 40% energy at 200 MHz compared to the static CMOS. And below 100 MHz CCAL eight-inverter chain always has lower dissipation than the QSERL implementation.

Original language	English
Title of host publication	ISOCC 2013 - 2013 International SoC Design Conference
Publisher	IEEE Computer Society
Pages	64-67
Number of pages	4
ISBN (Print)	9781479911417
DOIs	https://doi.org/10.1109/ISOCC.2013.6863986
Publication status	Published - 2013
Event	2013 International SoC Design Conference, ISOCC 2013 - Busan Duration: 2013 Nov 17 → 2013 Nov 19

Other

Other	2013 International SoC Design Conference, ISOCC 2013
City	Busan
Period	13/11/17 → 13/11/19

Keywords

adiabatic logic
CCAL
Clocked CMOS
inverter chain
low power

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/ISOCC.2013.6863986

Cite this

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title = "Clocked CMOS adiabatic logic with low-power dissipation",

abstract = "This paper presents a new low-power adiabatic logic structure called Clocked CMOS Adiabatic Logic (CCAL), which is based on the Clocked CMOS logic. CCAL is powered by two complementary sinusoidal supply clocks. To demonstrate the energy efficiency of CCAL, eight-inverter chain is simulated to show the energy comparison among CCAL, Quasi-Static Energy Recovery Logic (QSERL) and conventional static CMOS with the Rohm 0.18 μm process. The simulation results indicate that CCAL implementation reduces about 40% energy at 200 MHz compared to the static CMOS. And below 100 MHz CCAL eight-inverter chain always has lower dissipation than the QSERL implementation.",

keywords = "adiabatic logic, CCAL, Clocked CMOS, inverter chain, low power",

author = "He Li and Yimeng Zhang and Tsutomu Yoshihara",

year = "2013",

doi = "10.1109/ISOCC.2013.6863986",

language = "English",

isbn = "9781479911417",

pages = "64--67",

booktitle = "ISOCC 2013 - 2013 International SoC Design Conference",

publisher = "IEEE Computer Society",

note = "2013 International SoC Design Conference, ISOCC 2013 ; Conference date: 17-11-2013 Through 19-11-2013",

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TY - GEN

T1 - Clocked CMOS adiabatic logic with low-power dissipation

AU - Li, He

AU - Zhang, Yimeng

AU - Yoshihara, Tsutomu

PY - 2013

Y1 - 2013

N2 - This paper presents a new low-power adiabatic logic structure called Clocked CMOS Adiabatic Logic (CCAL), which is based on the Clocked CMOS logic. CCAL is powered by two complementary sinusoidal supply clocks. To demonstrate the energy efficiency of CCAL, eight-inverter chain is simulated to show the energy comparison among CCAL, Quasi-Static Energy Recovery Logic (QSERL) and conventional static CMOS with the Rohm 0.18 μm process. The simulation results indicate that CCAL implementation reduces about 40% energy at 200 MHz compared to the static CMOS. And below 100 MHz CCAL eight-inverter chain always has lower dissipation than the QSERL implementation.

AB - This paper presents a new low-power adiabatic logic structure called Clocked CMOS Adiabatic Logic (CCAL), which is based on the Clocked CMOS logic. CCAL is powered by two complementary sinusoidal supply clocks. To demonstrate the energy efficiency of CCAL, eight-inverter chain is simulated to show the energy comparison among CCAL, Quasi-Static Energy Recovery Logic (QSERL) and conventional static CMOS with the Rohm 0.18 μm process. The simulation results indicate that CCAL implementation reduces about 40% energy at 200 MHz compared to the static CMOS. And below 100 MHz CCAL eight-inverter chain always has lower dissipation than the QSERL implementation.

KW - adiabatic logic

KW - CCAL

KW - Clocked CMOS

KW - inverter chain

KW - low power

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DO - 10.1109/ISOCC.2013.6863986

M3 - Conference contribution

AN - SCOPUS:84906896017

SN - 9781479911417

SP - 64

EP - 67

BT - ISOCC 2013 - 2013 International SoC Design Conference

PB - IEEE Computer Society

T2 - 2013 International SoC Design Conference, ISOCC 2013

Y2 - 17 November 2013 through 19 November 2013

ER -

Clocked CMOS adiabatic logic with low-power dissipation

Abstract

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Keywords

ASJC Scopus subject areas

UN SDGs

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