CMOS low-power subthreshold reference voltage utilizing self-biased body effect

Hao Zhang, Yimeng Zhang, Mengshu Huang, Yoshihara Tsutomu

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    Two novel voltage reference using self-biased body effect are discussed in this paper. The proposed circuits based on the weighted difference of two gate-source voltages of two MOSFETs operated in subthreshold region and one of them with forward-biased body effect, can generate two ultra-low reference voltages of 171.1 mV and 243.2 mV with temperature coefficients of 15.6 ppm/°C and 14.8 ppm/°C in a range from -25°C∼80°C, respectively. The voltage line sensitivities are 0.0025%/V and 0.0019%/V. The power supply rejection ratio (PSRR) are -110 dB and -105 dB at 100 Hz. The power dissipations are 0.74 W and 1.4 μW at a 1.4-V power supply. The circuits were designed and simulated in 0.18 μm CMOS technology. The layouts illustrate the chip area are 0.016 mm 2 and 0.014 mm 2.

    Original languageEnglish
    Title of host publicationProceedings of International Conference on ASIC
    Pages516-519
    Number of pages4
    DOIs
    Publication statusPublished - 2011
    Event2011 IEEE 9th International Conference on ASIC, ASICON 2011 - Xiamen
    Duration: 2011 Oct 252011 Oct 28

    Other

    Other2011 IEEE 9th International Conference on ASIC, ASICON 2011
    CityXiamen
    Period11/10/2511/10/28

    Fingerprint

    Electric potential
    Networks (circuits)
    Energy dissipation
    Temperature

    Keywords

    • area efficient
    • body effect
    • CMOS voltage reference
    • low power
    • subthreshold

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

    Cite this

    Zhang, H., Zhang, Y., Huang, M., & Tsutomu, Y. (2011). CMOS low-power subthreshold reference voltage utilizing self-biased body effect. In Proceedings of International Conference on ASIC (pp. 516-519). [6157235] https://doi.org/10.1109/ASICON.2011.6157235

    CMOS low-power subthreshold reference voltage utilizing self-biased body effect. / Zhang, Hao; Zhang, Yimeng; Huang, Mengshu; Tsutomu, Yoshihara.

    Proceedings of International Conference on ASIC. 2011. p. 516-519 6157235.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Zhang, H, Zhang, Y, Huang, M & Tsutomu, Y 2011, CMOS low-power subthreshold reference voltage utilizing self-biased body effect. in Proceedings of International Conference on ASIC., 6157235, pp. 516-519, 2011 IEEE 9th International Conference on ASIC, ASICON 2011, Xiamen, 11/10/25. https://doi.org/10.1109/ASICON.2011.6157235
    Zhang H, Zhang Y, Huang M, Tsutomu Y. CMOS low-power subthreshold reference voltage utilizing self-biased body effect. In Proceedings of International Conference on ASIC. 2011. p. 516-519. 6157235 https://doi.org/10.1109/ASICON.2011.6157235
    Zhang, Hao ; Zhang, Yimeng ; Huang, Mengshu ; Tsutomu, Yoshihara. / CMOS low-power subthreshold reference voltage utilizing self-biased body effect. Proceedings of International Conference on ASIC. 2011. pp. 516-519
    @inproceedings{6fa03375222348ef93c0c2b6db033e49,
    title = "CMOS low-power subthreshold reference voltage utilizing self-biased body effect",
    abstract = "Two novel voltage reference using self-biased body effect are discussed in this paper. The proposed circuits based on the weighted difference of two gate-source voltages of two MOSFETs operated in subthreshold region and one of them with forward-biased body effect, can generate two ultra-low reference voltages of 171.1 mV and 243.2 mV with temperature coefficients of 15.6 ppm/°C and 14.8 ppm/°C in a range from -25°C∼80°C, respectively. The voltage line sensitivities are 0.0025{\%}/V and 0.0019{\%}/V. The power supply rejection ratio (PSRR) are -110 dB and -105 dB at 100 Hz. The power dissipations are 0.74 W and 1.4 μW at a 1.4-V power supply. The circuits were designed and simulated in 0.18 μm CMOS technology. The layouts illustrate the chip area are 0.016 mm 2 and 0.014 mm 2.",
    keywords = "area efficient, body effect, CMOS voltage reference, low power, subthreshold",
    author = "Hao Zhang and Yimeng Zhang and Mengshu Huang and Yoshihara Tsutomu",
    year = "2011",
    doi = "10.1109/ASICON.2011.6157235",
    language = "English",
    isbn = "9781612841908",
    pages = "516--519",
    booktitle = "Proceedings of International Conference on ASIC",

    }

    TY - GEN

    T1 - CMOS low-power subthreshold reference voltage utilizing self-biased body effect

    AU - Zhang, Hao

    AU - Zhang, Yimeng

    AU - Huang, Mengshu

    AU - Tsutomu, Yoshihara

    PY - 2011

    Y1 - 2011

    N2 - Two novel voltage reference using self-biased body effect are discussed in this paper. The proposed circuits based on the weighted difference of two gate-source voltages of two MOSFETs operated in subthreshold region and one of them with forward-biased body effect, can generate two ultra-low reference voltages of 171.1 mV and 243.2 mV with temperature coefficients of 15.6 ppm/°C and 14.8 ppm/°C in a range from -25°C∼80°C, respectively. The voltage line sensitivities are 0.0025%/V and 0.0019%/V. The power supply rejection ratio (PSRR) are -110 dB and -105 dB at 100 Hz. The power dissipations are 0.74 W and 1.4 μW at a 1.4-V power supply. The circuits were designed and simulated in 0.18 μm CMOS technology. The layouts illustrate the chip area are 0.016 mm 2 and 0.014 mm 2.

    AB - Two novel voltage reference using self-biased body effect are discussed in this paper. The proposed circuits based on the weighted difference of two gate-source voltages of two MOSFETs operated in subthreshold region and one of them with forward-biased body effect, can generate two ultra-low reference voltages of 171.1 mV and 243.2 mV with temperature coefficients of 15.6 ppm/°C and 14.8 ppm/°C in a range from -25°C∼80°C, respectively. The voltage line sensitivities are 0.0025%/V and 0.0019%/V. The power supply rejection ratio (PSRR) are -110 dB and -105 dB at 100 Hz. The power dissipations are 0.74 W and 1.4 μW at a 1.4-V power supply. The circuits were designed and simulated in 0.18 μm CMOS technology. The layouts illustrate the chip area are 0.016 mm 2 and 0.014 mm 2.

    KW - area efficient

    KW - body effect

    KW - CMOS voltage reference

    KW - low power

    KW - subthreshold

    UR - http://www.scopus.com/inward/record.url?scp=84860857082&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=84860857082&partnerID=8YFLogxK

    U2 - 10.1109/ASICON.2011.6157235

    DO - 10.1109/ASICON.2011.6157235

    M3 - Conference contribution

    AN - SCOPUS:84860857082

    SN - 9781612841908

    SP - 516

    EP - 519

    BT - Proceedings of International Conference on ASIC

    ER -