CMOS low-power subthreshold reference voltage utilizing self-biased body effect

Hao Zhang, Yimeng Zhang, Mengshu Huang, Yoshihara Tsutomu

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    Two novel voltage reference using self-biased body effect are discussed in this paper. The proposed circuits based on the weighted difference of two gate-source voltages of two MOSFETs operated in subthreshold region and one of them with forward-biased body effect, can generate two ultra-low reference voltages of 171.1 mV and 243.2 mV with temperature coefficients of 15.6 ppm/°C and 14.8 ppm/°C in a range from -25°C∼80°C, respectively. The voltage line sensitivities are 0.0025%/V and 0.0019%/V. The power supply rejection ratio (PSRR) are -110 dB and -105 dB at 100 Hz. The power dissipations are 0.74 W and 1.4 μW at a 1.4-V power supply. The circuits were designed and simulated in 0.18 μm CMOS technology. The layouts illustrate the chip area are 0.016 mm 2 and 0.014 mm 2.

    Original languageEnglish
    Title of host publicationProceedings of International Conference on ASIC
    Pages516-519
    Number of pages4
    DOIs
    Publication statusPublished - 2011
    Event2011 IEEE 9th International Conference on ASIC, ASICON 2011 - Xiamen
    Duration: 2011 Oct 252011 Oct 28

    Other

    Other2011 IEEE 9th International Conference on ASIC, ASICON 2011
    CityXiamen
    Period11/10/2511/10/28

    Keywords

    • area efficient
    • body effect
    • CMOS voltage reference
    • low power
    • subthreshold

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

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