COMPACTION BASED CUSTOM LSI LAYOUT DESIGN METHOD.

Masaki Ishikawa, Tsuneo Matsuda, Satoshi Goto

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    A new design method for custom LSI layouts is presented. This method is based on layout compaction with automatic jog (wiring bend) insertion in the layout. A dense chip design can be realized by this technique. Experimental results show that the resulting chip size is only 1. 2-1. 4 times larger than that resulting from manual layout. Therefore, this compaction-based custom LSI layout method is effective for achieving a minimal chip layout design.

    Original languageEnglish
    Title of host publicationUnknown Host Publication Title
    Place of PublicationNew York, NY, USA
    PublisherIEEE
    Pages343-345
    Number of pages3
    ISBN (Print)0818606878
    Publication statusPublished - 1985

    Fingerprint

    Compaction
    Electric wiring

    ASJC Scopus subject areas

    • Engineering(all)

    Cite this

    Ishikawa, M., Matsuda, T., & Goto, S. (1985). COMPACTION BASED CUSTOM LSI LAYOUT DESIGN METHOD. In Unknown Host Publication Title (pp. 343-345). New York, NY, USA: IEEE.

    COMPACTION BASED CUSTOM LSI LAYOUT DESIGN METHOD. / Ishikawa, Masaki; Matsuda, Tsuneo; Goto, Satoshi.

    Unknown Host Publication Title. New York, NY, USA : IEEE, 1985. p. 343-345.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Ishikawa, M, Matsuda, T & Goto, S 1985, COMPACTION BASED CUSTOM LSI LAYOUT DESIGN METHOD. in Unknown Host Publication Title. IEEE, New York, NY, USA, pp. 343-345.
    Ishikawa M, Matsuda T, Goto S. COMPACTION BASED CUSTOM LSI LAYOUT DESIGN METHOD. In Unknown Host Publication Title. New York, NY, USA: IEEE. 1985. p. 343-345
    Ishikawa, Masaki ; Matsuda, Tsuneo ; Goto, Satoshi. / COMPACTION BASED CUSTOM LSI LAYOUT DESIGN METHOD. Unknown Host Publication Title. New York, NY, USA : IEEE, 1985. pp. 343-345
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