Masaki Ishikawa, Tsuneo Matsuda, Takeshi Yoshimura, Satoshi Goto

Research output: Contribution to journalArticlepeer-review


A design method for custom LSI layouts is presented. This method is based on layout compaction with automatic jog (wiring bend) generation in the layout. A dense chip design can be realized by this technique. Experimental results show that the chip size designed by using the proposed layout method is only 1. 2-1. 4 times larger than that resulting from manual layouts. It is concluded that this compaction-based custom LSI layout design method is very effective for achieving a minimal chip layout design.

Original languageEnglish
Pages (from-to)374-382
Number of pages9
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number3
Publication statusPublished - 1987 May
Externally publishedYes

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Computer Science Applications
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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