Clock gating is a power efficient technique by switching off unnecessary clock signals to the registers. The condition under which the registers can be safely gated is checked using EXOR of the current and the next state values. Due to the extra power consumed by clock gating logics consisting of a latch and an AND gate, we have proposed an optimum sharing method of gating controls based on BDD (Binary Decision Diagram) with single-stage clock gating for power optimization. In this paper, we enhance the optimization method including multi-stage clock gating and compare with structural gating approach. By multi-stage clock gating, the activities of both registers and clock gating logics can be reduced. On a set of interface circuits, we have obtained power reduction by 14.1% on average compared with single-stage structural method and by 10.8% compared with multi-stage structural gating approach. Our BDD based method is also fast and scalable by candidates pruning.