Compiler control power saving scheme for multi core processors

Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    16 Citations (Scopus)

    Abstract

    With the increase of transistors integrated onto a chip, multi core processor architectures have attracted much attention to achieve high effective performance, shorten development period and reduce the power consumption. To this end, the compiler for a multi core processor is expected not only to parallelize program effectively, but also to control the voltage and clock frequency of processors and storages carefully inside an application program. This paper proposes a compilation scheme for reduction of power consumption under the multigrain parallel processing environment that controls Voltage/Frequency and power supply of each processor core on a chip. In the evaluation, the OSCAR compiler with the proposed scheme achieves 60.7 percent energy savings for SPEC CFP95 applu without performance degradation on 4 processors, and 45.4 percent energy savings for SPEC CFP95 tomcatv with real-time deadline constraint on 4 processors, and 46.5 percent energy savings for SPEC CFP95 swim with the deadline constraint on 4 processors.

    Original languageEnglish
    Title of host publicationLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
    Pages362-376
    Number of pages15
    Volume4339 LNCS
    DOIs
    Publication statusPublished - 2006
    Event18th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2005 - Hawthorne, NY
    Duration: 2005 Oct 202005 Oct 22

    Publication series

    NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
    Volume4339 LNCS
    ISSN (Print)03029743
    ISSN (Electronic)16113349

    Other

    Other18th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2005
    CityHawthorne, NY
    Period05/10/2005/10/22

    Fingerprint

    Electric Power Supplies
    Power Saving
    Multi-core Processor
    Energy Saving
    Power control
    Compiler
    Percent
    Energy conservation
    Deadline
    Power Consumption
    Electric power utilization
    Chip
    Voltage
    Compilation
    Parallel Processing
    Application programs
    Voltage control
    Clocks
    Transistors
    Degradation

    ASJC Scopus subject areas

    • Computer Science(all)
    • Biochemistry, Genetics and Molecular Biology(all)
    • Theoretical Computer Science

    Cite this

    Shirako, J., Oshiyama, N., Wada, Y., Shikano, H., Kimura, K., & Kasahara, H. (2006). Compiler control power saving scheme for multi core processors. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 4339 LNCS, pp. 362-376). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4339 LNCS). https://doi.org/10.1007/978-3-540-69330-7_25

    Compiler control power saving scheme for multi core processors. / Shirako, Jun; Oshiyama, Naoto; Wada, Yasutaka; Shikano, Hiroaki; Kimura, Keiji; Kasahara, Hironori.

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 4339 LNCS 2006. p. 362-376 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4339 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Shirako, J, Oshiyama, N, Wada, Y, Shikano, H, Kimura, K & Kasahara, H 2006, Compiler control power saving scheme for multi core processors. in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). vol. 4339 LNCS, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 4339 LNCS, pp. 362-376, 18th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2005, Hawthorne, NY, 05/10/20. https://doi.org/10.1007/978-3-540-69330-7_25
    Shirako J, Oshiyama N, Wada Y, Shikano H, Kimura K, Kasahara H. Compiler control power saving scheme for multi core processors. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 4339 LNCS. 2006. p. 362-376. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). https://doi.org/10.1007/978-3-540-69330-7_25
    Shirako, Jun ; Oshiyama, Naoto ; Wada, Yasutaka ; Shikano, Hiroaki ; Kimura, Keiji ; Kasahara, Hironori. / Compiler control power saving scheme for multi core processors. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 4339 LNCS 2006. pp. 362-376 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).
    @inproceedings{c1823afba3d745539251e36b02e06b41,
    title = "Compiler control power saving scheme for multi core processors",
    abstract = "With the increase of transistors integrated onto a chip, multi core processor architectures have attracted much attention to achieve high effective performance, shorten development period and reduce the power consumption. To this end, the compiler for a multi core processor is expected not only to parallelize program effectively, but also to control the voltage and clock frequency of processors and storages carefully inside an application program. This paper proposes a compilation scheme for reduction of power consumption under the multigrain parallel processing environment that controls Voltage/Frequency and power supply of each processor core on a chip. In the evaluation, the OSCAR compiler with the proposed scheme achieves 60.7 percent energy savings for SPEC CFP95 applu without performance degradation on 4 processors, and 45.4 percent energy savings for SPEC CFP95 tomcatv with real-time deadline constraint on 4 processors, and 46.5 percent energy savings for SPEC CFP95 swim with the deadline constraint on 4 processors.",
    author = "Jun Shirako and Naoto Oshiyama and Yasutaka Wada and Hiroaki Shikano and Keiji Kimura and Hironori Kasahara",
    year = "2006",
    doi = "10.1007/978-3-540-69330-7_25",
    language = "English",
    isbn = "3540693297",
    volume = "4339 LNCS",
    series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",
    pages = "362--376",
    booktitle = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

    }

    TY - GEN

    T1 - Compiler control power saving scheme for multi core processors

    AU - Shirako, Jun

    AU - Oshiyama, Naoto

    AU - Wada, Yasutaka

    AU - Shikano, Hiroaki

    AU - Kimura, Keiji

    AU - Kasahara, Hironori

    PY - 2006

    Y1 - 2006

    N2 - With the increase of transistors integrated onto a chip, multi core processor architectures have attracted much attention to achieve high effective performance, shorten development period and reduce the power consumption. To this end, the compiler for a multi core processor is expected not only to parallelize program effectively, but also to control the voltage and clock frequency of processors and storages carefully inside an application program. This paper proposes a compilation scheme for reduction of power consumption under the multigrain parallel processing environment that controls Voltage/Frequency and power supply of each processor core on a chip. In the evaluation, the OSCAR compiler with the proposed scheme achieves 60.7 percent energy savings for SPEC CFP95 applu without performance degradation on 4 processors, and 45.4 percent energy savings for SPEC CFP95 tomcatv with real-time deadline constraint on 4 processors, and 46.5 percent energy savings for SPEC CFP95 swim with the deadline constraint on 4 processors.

    AB - With the increase of transistors integrated onto a chip, multi core processor architectures have attracted much attention to achieve high effective performance, shorten development period and reduce the power consumption. To this end, the compiler for a multi core processor is expected not only to parallelize program effectively, but also to control the voltage and clock frequency of processors and storages carefully inside an application program. This paper proposes a compilation scheme for reduction of power consumption under the multigrain parallel processing environment that controls Voltage/Frequency and power supply of each processor core on a chip. In the evaluation, the OSCAR compiler with the proposed scheme achieves 60.7 percent energy savings for SPEC CFP95 applu without performance degradation on 4 processors, and 45.4 percent energy savings for SPEC CFP95 tomcatv with real-time deadline constraint on 4 processors, and 46.5 percent energy savings for SPEC CFP95 swim with the deadline constraint on 4 processors.

    UR - http://www.scopus.com/inward/record.url?scp=43949122214&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=43949122214&partnerID=8YFLogxK

    U2 - 10.1007/978-3-540-69330-7_25

    DO - 10.1007/978-3-540-69330-7_25

    M3 - Conference contribution

    AN - SCOPUS:43949122214

    SN - 3540693297

    SN - 9783540693291

    VL - 4339 LNCS

    T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

    SP - 362

    EP - 376

    BT - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

    ER -