Compiler control power saving scheme for multi core processors

Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)

Abstract

With the increase of transistors integrated onto a chip, multi core processor architectures have attracted much attention to achieve high effective performance, shorten development period and reduce the power consumption. To this end, the compiler for a multi core processor is expected not only to parallelize program effectively, but also to control the voltage and clock frequency of processors and storages carefully inside an application program. This paper proposes a compilation scheme for reduction of power consumption under the multigrain parallel processing environment that controls Voltage/Frequency and power supply of each processor core on a chip. In the evaluation, the OSCAR compiler with the proposed scheme achieves 60.7 percent energy savings for SPEC CFP95 applu without performance degradation on 4 processors, and 45.4 percent energy savings for SPEC CFP95 tomcatv with real-time deadline constraint on 4 processors, and 46.5 percent energy savings for SPEC CFP95 swim with the deadline constraint on 4 processors.

Original languageEnglish
Title of host publicationLanguages and Compilers for Parallel Computing - 18th International Workshop, LCPC 2005, Revised Selected Papers
Pages362-376
Number of pages15
DOIs
Publication statusPublished - 2006 Dec 1
Event18th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2005 - Hawthorne, NY, United States
Duration: 2005 Oct 202005 Oct 22

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume4339 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference18th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2005
CountryUnited States
CityHawthorne, NY
Period05/10/2005/10/22

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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    Shirako, J., Oshiyama, N., Wada, Y., Shikano, H., Kimura, K., & Kasahara, H. (2006). Compiler control power saving scheme for multi core processors. In Languages and Compilers for Parallel Computing - 18th International Workshop, LCPC 2005, Revised Selected Papers (pp. 362-376). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4339 LNCS). https://doi.org/10.1007/978-3-540-69330-7_25