Racetrack memories (RMs) are prone to alignment faults called position errors (PEs), which manifest as insertions and deletions of stored data bits. Conventional coding schemes for PEs demonstrate the promising results by employing low-density parity-check (LDPC) codes with an iterative detection and decoding algorithm. However, the computational complexity of detection is relatively high. In this article, for channels with PEs, we present a new coding scheme that can effectively decode corrupted data, even if the detection is executed only once (i.e., a non-iterative detection and decoding scenario). The proposed code consists of a concatenation of an inner 2-D marker code, which is specialized for PEs to mitigate the effect of insertion and deletion (ID) errors, and an outer irregular LDPC code. We also provide tractable design methodologies for these constituent codes. First, we identify the 2-D-marker code structures that offer higher achievable information rates in a non-iterative scenario and then optimize irregular LDPC codes to ensure good decoding properties. Through asymptotic-performance analysis and finite-length simulation, we confirm the effectiveness of the proposed coding scheme. Ultimately, the proposed coding scheme has the capability to reduce code rate loss and to provide excellent decoding performance under a non-iterative scenario, which also helps in understanding the reliability of RM when a low-complexity decoding algorithm is used to correct ID errors caused by PEs.
- Low-density parity-check (LDPC) codes
- position error (PE)
- racetrack memories (RMs)
- synchronization marker
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering