Concurrent faulty clock detection for crypto circuits against clock glitch based DFA

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

In this paper, a concurrent faulty clock detection method is proposed for crypto circuits against clock glitch based differential fault analysis (DFA). In the proposed method, a nonlogic buffer-based delay chain is inserted, and then by monitoring the delay along the delay chain, a possible clock glitch based DFA can be detected. Experimental results on an AES circuit show that the proposed method can successfully detect clock glitch based attacks, and the required area overhead is only 0.47% that is much smaller than previous works.

Original languageEnglish
Title of host publication2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Pages1432-1435
Number of pages4
DOIs
Publication statusPublished - 2013 Sep 9
Event2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing, China
Duration: 2013 May 192013 May 23

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
CountryChina
CityBeijing
Period13/5/1913/5/23

Keywords

  • advanced encryption standard
  • clock glitch
  • crypto circuit
  • differential fault attack
  • side-channel attacks

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Igarashi, H., Shi, Y., Yanagisawa, M., & Togawa, N. (2013). Concurrent faulty clock detection for crypto circuits against clock glitch based DFA. In 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 (pp. 1432-1435). [6572125] (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2013.6572125