Abstract
The correlation between the static random access memory (SRAM) power-up state (i.e., state 0 or 1 immediately after the power supply is turned on) and cell transistor variation is systematically studied by circuit simulations and mismatch space partitioning. It is revealed that, while both the mismatches of pFETs (pull-up) and nFETs (pull-down and access) contribute, their relative importance changes depending on the voltage ramping speed. The static retention noise margin well correlates with the power-up state only if the ramping speed is sufficiently low. Otherwise, pull-up transistor mismatch dominates the power-up state determination owing to the interference of capacitive current and asymmetrical capacitive coupling of the storage nodes to the ground and power supply.
| Original language | English |
|---|---|
| Article number | 04CD03 |
| Journal | Japanese Journal of Applied Physics |
| Volume | 56 |
| Issue number | 4 |
| DOIs | |
| Publication status | Published - 2017 Apr 1 |
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ASJC Scopus subject areas
- Engineering(all)
- Physics and Astronomy(all)
Cite this
Correlation between static random access memory power-up state and transistor variation. / Takeuchi, Kiyoshi; Mizutani, Tomoko; Saraya, Takuya; Shinohara, Hirofumi; Kobayashi, Masaharu; Hiramoto, Toshiro.
In: Japanese Journal of Applied Physics, Vol. 56, No. 4, 04CD03, 01.04.2017.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Correlation between static random access memory power-up state and transistor variation
AU - Takeuchi, Kiyoshi
AU - Mizutani, Tomoko
AU - Saraya, Takuya
AU - Shinohara, Hirofumi
AU - Kobayashi, Masaharu
AU - Hiramoto, Toshiro
PY - 2017/4/1
Y1 - 2017/4/1
N2 - The correlation between the static random access memory (SRAM) power-up state (i.e., state 0 or 1 immediately after the power supply is turned on) and cell transistor variation is systematically studied by circuit simulations and mismatch space partitioning. It is revealed that, while both the mismatches of pFETs (pull-up) and nFETs (pull-down and access) contribute, their relative importance changes depending on the voltage ramping speed. The static retention noise margin well correlates with the power-up state only if the ramping speed is sufficiently low. Otherwise, pull-up transistor mismatch dominates the power-up state determination owing to the interference of capacitive current and asymmetrical capacitive coupling of the storage nodes to the ground and power supply.
AB - The correlation between the static random access memory (SRAM) power-up state (i.e., state 0 or 1 immediately after the power supply is turned on) and cell transistor variation is systematically studied by circuit simulations and mismatch space partitioning. It is revealed that, while both the mismatches of pFETs (pull-up) and nFETs (pull-down and access) contribute, their relative importance changes depending on the voltage ramping speed. The static retention noise margin well correlates with the power-up state only if the ramping speed is sufficiently low. Otherwise, pull-up transistor mismatch dominates the power-up state determination owing to the interference of capacitive current and asymmetrical capacitive coupling of the storage nodes to the ground and power supply.
UR - http://www.scopus.com/inward/record.url?scp=85017162856&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85017162856&partnerID=8YFLogxK
U2 - 10.7567/JJAP.56.04CD03
DO - 10.7567/JJAP.56.04CD03
M3 - Article
AN - SCOPUS:85017162856
VL - 56
JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
SN - 0021-4922
IS - 4
M1 - 04CD03
ER -