Abstract
This paper proposes an improved Message Passing schedule for irregular LDPC decoder. Redundant memory accesses and column operations are removed by utilizing the characteristics of partial-parallel irregular LDPC decoding algorithm. As a result, the memory access frequency and hardware cost are efficiently reduced. According to the experimental results and comparison with existing work, proposed decoder provides a 30% hardware area reduction and a 36% power consumption saving with the same error correcting performance.
| Original language | English |
|---|---|
| Title of host publication | 2007 International Symposium on Integrated Circuits, ISIC |
| Pages | 508-511 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2007 Dec 1 |
| Event | 2007 International Symposium on Integrated Circuits, ISIC - Singapore, Singapore Duration: 2007 Sep 26 → 2007 Sep 28 |
Publication series
| Name | 2007 International Symposium on Integrated Circuits, ISIC |
|---|
Conference
| Conference | 2007 International Symposium on Integrated Circuits, ISIC |
|---|---|
| Country | Singapore |
| City | Singapore |
| Period | 07/9/26 → 07/9/28 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
Fingerprint Dive into the research topics of 'Cost-efficient partially-parallel irregular LDPC decoder with message passing schedule'. Together they form a unique fingerprint.
Cite this
Li, X., Abe, Y., Shimizu, K., Qiu, Z., Ikenaga, T., & Goto, S. (2007). Cost-efficient partially-parallel irregular LDPC decoder with message passing schedule. In 2007 International Symposium on Integrated Circuits, ISIC (pp. 508-511). [4441910] (2007 International Symposium on Integrated Circuits, ISIC). https://doi.org/10.1109/ISICIR.2007.4441910