TY - GEN
T1 - Cost-efficient partially-parallel irregular LDPC decoder with message passing schedule
AU - Li, Xing
AU - Abe, Yuta
AU - Shimizu, Kazunori
AU - Qiu, Zhen
AU - Ikenaga, Takeshi
AU - Goto, Satoshi
PY - 2007/12/1
Y1 - 2007/12/1
N2 - This paper proposes an improved Message Passing schedule for irregular LDPC decoder. Redundant memory accesses and column operations are removed by utilizing the characteristics of partial-parallel irregular LDPC decoding algorithm. As a result, the memory access frequency and hardware cost are efficiently reduced. According to the experimental results and comparison with existing work, proposed decoder provides a 30% hardware area reduction and a 36% power consumption saving with the same error correcting performance.
AB - This paper proposes an improved Message Passing schedule for irregular LDPC decoder. Redundant memory accesses and column operations are removed by utilizing the characteristics of partial-parallel irregular LDPC decoding algorithm. As a result, the memory access frequency and hardware cost are efficiently reduced. According to the experimental results and comparison with existing work, proposed decoder provides a 30% hardware area reduction and a 36% power consumption saving with the same error correcting performance.
UR - http://www.scopus.com/inward/record.url?scp=51549095970&partnerID=8YFLogxK
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U2 - 10.1109/ISICIR.2007.4441910
DO - 10.1109/ISICIR.2007.4441910
M3 - Conference contribution
AN - SCOPUS:51549095970
SN - 1424407974
SN - 9781424407972
T3 - 2007 International Symposium on Integrated Circuits, ISIC
SP - 508
EP - 511
BT - 2007 International Symposium on Integrated Circuits, ISIC
T2 - 2007 International Symposium on Integrated Circuits, ISIC
Y2 - 26 September 2007 through 28 September 2007
ER -