Cost-efficient partially-parallel irregular LDPC decoder with message passing schedule

Xing Li, Yuta Abe, Kazunori Shimizu, Zhen Qiu, Takeshi Ikenaga, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

This paper proposes an improved Message Passing schedule for irregular LDPC decoder. Redundant memory accesses and column operations are removed by utilizing the characteristics of partial-parallel irregular LDPC decoding algorithm. As a result, the memory access frequency and hardware cost are efficiently reduced. According to the experimental results and comparison with existing work, proposed decoder provides a 30% hardware area reduction and a 36% power consumption saving with the same error correcting performance.

Original languageEnglish
Title of host publication2007 International Symposium on Integrated Circuits, ISIC
Pages508-511
Number of pages4
DOIs
Publication statusPublished - 2007
Event2007 International Symposium on Integrated Circuits, ISIC - Singapore
Duration: 2007 Sep 26 → 2007 Sep 28

Other

Other2007 International Symposium on Integrated Circuits, ISIC
CitySingapore
Period07/9/26 → 07/9/28

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Message passing
Data storage equipment
Computer hardware
Decoding
Costs
Electric power utilization
Hardware

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Li, X., Abe, Y., Shimizu, K., Qiu, Z., Ikenaga, T., & Goto, S. (2007). Cost-efficient partially-parallel irregular LDPC decoder with message passing schedule. In 2007 International Symposium on Integrated Circuits, ISIC (pp. 508-511). [4441910] https://doi.org/10.1109/ISICIR.2007.4441910

Cost-efficient partially-parallel irregular LDPC decoder with message passing schedule. / Li, Xing; Abe, Yuta; Shimizu, Kazunori; Qiu, Zhen; Ikenaga, Takeshi; Goto, Satoshi.

2007 International Symposium on Integrated Circuits, ISIC. 2007. p. 508-511 4441910.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Li, X, Abe, Y, Shimizu, K, Qiu, Z, Ikenaga, T & Goto, S 2007, Cost-efficient partially-parallel irregular LDPC decoder with message passing schedule. in 2007 International Symposium on Integrated Circuits, ISIC., 4441910, pp. 508-511, 2007 International Symposium on Integrated Circuits, ISIC, Singapore, 07/9/26. https://doi.org/10.1109/ISICIR.2007.4441910
Li X, Abe Y, Shimizu K, Qiu Z, Ikenaga T, Goto S. Cost-efficient partially-parallel irregular LDPC decoder with message passing schedule. In 2007 International Symposium on Integrated Circuits, ISIC. 2007. p. 508-511. 4441910 https://doi.org/10.1109/ISICIR.2007.4441910
Li, Xing ; Abe, Yuta ; Shimizu, Kazunori ; Qiu, Zhen ; Ikenaga, Takeshi ; Goto, Satoshi. / Cost-efficient partially-parallel irregular LDPC decoder with message passing schedule. 2007 International Symposium on Integrated Circuits, ISIC. 2007. pp. 508-511
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