Cost-efficient partially-parallel irregular LDPC decoder with message passing schedule

Xing Li; Yuta Abe; Kazunori Shimizu; Zhen Qiu; Takeshi Ikenaga; Satoshi Goto

doi:10.1109/ISICIR.2007.4441910

Cost-efficient partially-parallel irregular LDPC decoder with message passing schedule

Xing Li^*, Yuta Abe, Kazunori Shimizu, Zhen Qiu, Takeshi Ikenaga, Satoshi Goto

^*Corresponding author for this work

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

This paper proposes an improved Message Passing schedule for irregular LDPC decoder. Redundant memory accesses and column operations are removed by utilizing the characteristics of partial-parallel irregular LDPC decoding algorithm. As a result, the memory access frequency and hardware cost are efficiently reduced. According to the experimental results and comparison with existing work, proposed decoder provides a 30% hardware area reduction and a 36% power consumption saving with the same error correcting performance.

Original language	English
Title of host publication	2007 International Symposium on Integrated Circuits, ISIC
Pages	508-511
Number of pages	4
DOIs	https://doi.org/10.1109/ISICIR.2007.4441910
Publication status	Published - 2007 Dec 1
Event	2007 International Symposium on Integrated Circuits, ISIC - Singapore, Singapore Duration: 2007 Sep 26 → 2007 Sep 28

Publication series

Name	2007 International Symposium on Integrated Circuits, ISIC

Conference

Conference	2007 International Symposium on Integrated Circuits, ISIC
Country/Territory	Singapore
City	Singapore
Period	07/9/26 → 07/9/28

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISICIR.2007.4441910

Cite this

Cost-efficient partially-parallel irregular LDPC decoder with message passing schedule. / Li, Xing; Abe, Yuta; Shimizu, Kazunori; Qiu, Zhen; Ikenaga, Takeshi; Goto, Satoshi.

2007 International Symposium on Integrated Circuits, ISIC. 2007. p. 508-511 4441910 (2007 International Symposium on Integrated Circuits, ISIC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Li, X, Abe, Y, Shimizu, K, Qiu, Z, Ikenaga, T & Goto, S 2007, Cost-efficient partially-parallel irregular LDPC decoder with message passing schedule. in 2007 International Symposium on Integrated Circuits, ISIC., 4441910, 2007 International Symposium on Integrated Circuits, ISIC, pp. 508-511, 2007 International Symposium on Integrated Circuits, ISIC, Singapore, Singapore, 07/9/26. https://doi.org/10.1109/ISICIR.2007.4441910

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AU - Goto, Satoshi

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AB - This paper proposes an improved Message Passing schedule for irregular LDPC decoder. Redundant memory accesses and column operations are removed by utilizing the characteristics of partial-parallel irregular LDPC decoding algorithm. As a result, the memory access frequency and hardware cost are efficiently reduced. According to the experimental results and comparison with existing work, proposed decoder provides a 30% hardware area reduction and a 36% power consumption saving with the same error correcting performance.

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Cost-efficient partially-parallel irregular LDPC decoder with message passing schedule

Abstract

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Conference

ASJC Scopus subject areas

Access to Document

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