Cost-efficient partially-parallel irregular LDPC decoder with message passing schedule

Xing Li, Yuta Abe, Kazunori Shimizu, Zhen Qiu, Takeshi Ikenaga, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

This paper proposes an improved Message Passing schedule for irregular LDPC decoder. Redundant memory accesses and column operations are removed by utilizing the characteristics of partial-parallel irregular LDPC decoding algorithm. As a result, the memory access frequency and hardware cost are efficiently reduced. According to the experimental results and comparison with existing work, proposed decoder provides a 30% hardware area reduction and a 36% power consumption saving with the same error correcting performance.

Original languageEnglish
Title of host publication2007 International Symposium on Integrated Circuits, ISIC
Pages508-511
Number of pages4
DOIs
Publication statusPublished - 2007 Dec 1
Event2007 International Symposium on Integrated Circuits, ISIC - Singapore, Singapore
Duration: 2007 Sep 262007 Sep 28

Publication series

Name2007 International Symposium on Integrated Circuits, ISIC

Conference

Conference2007 International Symposium on Integrated Circuits, ISIC
CountrySingapore
CitySingapore
Period07/9/2607/9/28

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Li, X., Abe, Y., Shimizu, K., Qiu, Z., Ikenaga, T., & Goto, S. (2007). Cost-efficient partially-parallel irregular LDPC decoder with message passing schedule. In 2007 International Symposium on Integrated Circuits, ISIC (pp. 508-511). [4441910] (2007 International Symposium on Integrated Circuits, ISIC). https://doi.org/10.1109/ISICIR.2007.4441910