Cost efficient propagate partial SAD architecture for integer motion estimation in H.264/AVC

Yiqing Huang, Zhenyu Liu, Satoshi Goto, Takeshi Ikenaga

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

The latest video coding standard H.264/AVC covers a wide range of applications from QCIF to HDTV. In case of HDTV, subsampling technique is widely adopted to reduce hardware cost with little video quality degradation. Moreover, experiments show that contribution of small inter search modes to video quality is trivial so that mode reduction can help to further reduce hardware cost. This paper proposes a cost efficient Propagate Partial SAD architecture for HDTV application. The highly pipelined feature of proposed architecture makes it robust to high speed impact. Compared with widely used SAD Tree structure, the proposed cost efficient structure which adopts subsampling and inter search mode reduction can reduce averagely 23.88% hardware cost with negligible video quality loss. With TSMC 0.18μm CMOS 1P6M standard cell library, the maximum clock speed of this design is 233 MHz in worst work condition (1.62, 125°C).

Original languageEnglish
Title of host publicationASICON 2007 - 2007 7th International Conference on ASIC Proceeding
Pages782-785
Number of pages4
DOIs
Publication statusPublished - 2007
Event2007 7th International Conference on ASIC, ASICON 2007 - Guilin
Duration: 2007 Oct 262007 Oct 29

Other

Other2007 7th International Conference on ASIC, ASICON 2007
CityGuilin
Period07/10/2607/10/29

Fingerprint

Motion estimation
High definition television
Costs
Hardware
Image coding
Clocks
Degradation
Experiments

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Huang, Y., Liu, Z., Goto, S., & Ikenaga, T. (2007). Cost efficient propagate partial SAD architecture for integer motion estimation in H.264/AVC. In ASICON 2007 - 2007 7th International Conference on ASIC Proceeding (pp. 782-785). [4415747] https://doi.org/10.1109/ICASIC.2007.4415747

Cost efficient propagate partial SAD architecture for integer motion estimation in H.264/AVC. / Huang, Yiqing; Liu, Zhenyu; Goto, Satoshi; Ikenaga, Takeshi.

ASICON 2007 - 2007 7th International Conference on ASIC Proceeding. 2007. p. 782-785 4415747.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Huang, Y, Liu, Z, Goto, S & Ikenaga, T 2007, Cost efficient propagate partial SAD architecture for integer motion estimation in H.264/AVC. in ASICON 2007 - 2007 7th International Conference on ASIC Proceeding., 4415747, pp. 782-785, 2007 7th International Conference on ASIC, ASICON 2007, Guilin, 07/10/26. https://doi.org/10.1109/ICASIC.2007.4415747
Huang Y, Liu Z, Goto S, Ikenaga T. Cost efficient propagate partial SAD architecture for integer motion estimation in H.264/AVC. In ASICON 2007 - 2007 7th International Conference on ASIC Proceeding. 2007. p. 782-785. 4415747 https://doi.org/10.1109/ICASIC.2007.4415747
Huang, Yiqing ; Liu, Zhenyu ; Goto, Satoshi ; Ikenaga, Takeshi. / Cost efficient propagate partial SAD architecture for integer motion estimation in H.264/AVC. ASICON 2007 - 2007 7th International Conference on ASIC Proceeding. 2007. pp. 782-785
@inproceedings{c8103c6d99fd4f36bb69bed8580cb792,
title = "Cost efficient propagate partial SAD architecture for integer motion estimation in H.264/AVC",
abstract = "The latest video coding standard H.264/AVC covers a wide range of applications from QCIF to HDTV. In case of HDTV, subsampling technique is widely adopted to reduce hardware cost with little video quality degradation. Moreover, experiments show that contribution of small inter search modes to video quality is trivial so that mode reduction can help to further reduce hardware cost. This paper proposes a cost efficient Propagate Partial SAD architecture for HDTV application. The highly pipelined feature of proposed architecture makes it robust to high speed impact. Compared with widely used SAD Tree structure, the proposed cost efficient structure which adopts subsampling and inter search mode reduction can reduce averagely 23.88{\%} hardware cost with negligible video quality loss. With TSMC 0.18μm CMOS 1P6M standard cell library, the maximum clock speed of this design is 233 MHz in worst work condition (1.62, 125°C).",
author = "Yiqing Huang and Zhenyu Liu and Satoshi Goto and Takeshi Ikenaga",
year = "2007",
doi = "10.1109/ICASIC.2007.4415747",
language = "English",
isbn = "1424411327",
pages = "782--785",
booktitle = "ASICON 2007 - 2007 7th International Conference on ASIC Proceeding",

}

TY - GEN

T1 - Cost efficient propagate partial SAD architecture for integer motion estimation in H.264/AVC

AU - Huang, Yiqing

AU - Liu, Zhenyu

AU - Goto, Satoshi

AU - Ikenaga, Takeshi

PY - 2007

Y1 - 2007

N2 - The latest video coding standard H.264/AVC covers a wide range of applications from QCIF to HDTV. In case of HDTV, subsampling technique is widely adopted to reduce hardware cost with little video quality degradation. Moreover, experiments show that contribution of small inter search modes to video quality is trivial so that mode reduction can help to further reduce hardware cost. This paper proposes a cost efficient Propagate Partial SAD architecture for HDTV application. The highly pipelined feature of proposed architecture makes it robust to high speed impact. Compared with widely used SAD Tree structure, the proposed cost efficient structure which adopts subsampling and inter search mode reduction can reduce averagely 23.88% hardware cost with negligible video quality loss. With TSMC 0.18μm CMOS 1P6M standard cell library, the maximum clock speed of this design is 233 MHz in worst work condition (1.62, 125°C).

AB - The latest video coding standard H.264/AVC covers a wide range of applications from QCIF to HDTV. In case of HDTV, subsampling technique is widely adopted to reduce hardware cost with little video quality degradation. Moreover, experiments show that contribution of small inter search modes to video quality is trivial so that mode reduction can help to further reduce hardware cost. This paper proposes a cost efficient Propagate Partial SAD architecture for HDTV application. The highly pipelined feature of proposed architecture makes it robust to high speed impact. Compared with widely used SAD Tree structure, the proposed cost efficient structure which adopts subsampling and inter search mode reduction can reduce averagely 23.88% hardware cost with negligible video quality loss. With TSMC 0.18μm CMOS 1P6M standard cell library, the maximum clock speed of this design is 233 MHz in worst work condition (1.62, 125°C).

UR - http://www.scopus.com/inward/record.url?scp=48349121263&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=48349121263&partnerID=8YFLogxK

U2 - 10.1109/ICASIC.2007.4415747

DO - 10.1109/ICASIC.2007.4415747

M3 - Conference contribution

AN - SCOPUS:48349121263

SN - 1424411327

SN - 9781424411320

SP - 782

EP - 785

BT - ASICON 2007 - 2007 7th International Conference on ASIC Proceeding

ER -