CUSTOM CELL ARRAY APPROACH TO VLSI LAYOUT.

F. Kitajima, K. Takamizawa, H. Nakamura, N. Sugiyama, S. Goto

    Research output: Contribution to journalArticle

    2 Citations (Scopus)

    Abstract

    The authors describe a new approach to custom LSI layout. This approach, called custom cell array, has a big advantage over conventional custom design approaches, incorporating custom cell array generator, automatic or interactive layout programs and a chip image optimizer. Several experimental results are shown, indicating the effectiveness of the approach. A 12% reduction in layout area size is achieved, compared with a conventional poly cell layout approach, and a 29-62% reduction is achieved, compared with the gate array approach.

    Original languageEnglish
    Pages (from-to)395-398
    Number of pages4
    JournalUnknown Journal
    Publication statusPublished - 1985

    Fingerprint

    very large scale integration
    layouts
    cells
    large scale integration
    generators
    chips

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Electronic, Optical and Magnetic Materials

    Cite this

    Kitajima, F., Takamizawa, K., Nakamura, H., Sugiyama, N., & Goto, S. (1985). CUSTOM CELL ARRAY APPROACH TO VLSI LAYOUT. Unknown Journal, 395-398.

    CUSTOM CELL ARRAY APPROACH TO VLSI LAYOUT. / Kitajima, F.; Takamizawa, K.; Nakamura, H.; Sugiyama, N.; Goto, S.

    In: Unknown Journal, 1985, p. 395-398.

    Research output: Contribution to journalArticle

    Kitajima, F, Takamizawa, K, Nakamura, H, Sugiyama, N & Goto, S 1985, 'CUSTOM CELL ARRAY APPROACH TO VLSI LAYOUT.', Unknown Journal, pp. 395-398.
    Kitajima F, Takamizawa K, Nakamura H, Sugiyama N, Goto S. CUSTOM CELL ARRAY APPROACH TO VLSI LAYOUT. Unknown Journal. 1985;395-398.
    Kitajima, F. ; Takamizawa, K. ; Nakamura, H. ; Sugiyama, N. ; Goto, S. / CUSTOM CELL ARRAY APPROACH TO VLSI LAYOUT. In: Unknown Journal. 1985 ; pp. 395-398.
    @article{de0225b3e1de4d028de17ffbadee5a30,
    title = "CUSTOM CELL ARRAY APPROACH TO VLSI LAYOUT.",
    abstract = "The authors describe a new approach to custom LSI layout. This approach, called custom cell array, has a big advantage over conventional custom design approaches, incorporating custom cell array generator, automatic or interactive layout programs and a chip image optimizer. Several experimental results are shown, indicating the effectiveness of the approach. A 12{\%} reduction in layout area size is achieved, compared with a conventional poly cell layout approach, and a 29-62{\%} reduction is achieved, compared with the gate array approach.",
    author = "F. Kitajima and K. Takamizawa and H. Nakamura and N. Sugiyama and S. Goto",
    year = "1985",
    language = "English",
    pages = "395--398",
    journal = "Nuclear Physics A",
    issn = "0375-9474",
    publisher = "Elsevier",

    }

    TY - JOUR

    T1 - CUSTOM CELL ARRAY APPROACH TO VLSI LAYOUT.

    AU - Kitajima, F.

    AU - Takamizawa, K.

    AU - Nakamura, H.

    AU - Sugiyama, N.

    AU - Goto, S.

    PY - 1985

    Y1 - 1985

    N2 - The authors describe a new approach to custom LSI layout. This approach, called custom cell array, has a big advantage over conventional custom design approaches, incorporating custom cell array generator, automatic or interactive layout programs and a chip image optimizer. Several experimental results are shown, indicating the effectiveness of the approach. A 12% reduction in layout area size is achieved, compared with a conventional poly cell layout approach, and a 29-62% reduction is achieved, compared with the gate array approach.

    AB - The authors describe a new approach to custom LSI layout. This approach, called custom cell array, has a big advantage over conventional custom design approaches, incorporating custom cell array generator, automatic or interactive layout programs and a chip image optimizer. Several experimental results are shown, indicating the effectiveness of the approach. A 12% reduction in layout area size is achieved, compared with a conventional poly cell layout approach, and a 29-62% reduction is achieved, compared with the gate array approach.

    UR - http://www.scopus.com/inward/record.url?scp=0022307080&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=0022307080&partnerID=8YFLogxK

    M3 - Article

    SP - 395

    EP - 398

    JO - Nuclear Physics A

    JF - Nuclear Physics A

    SN - 0375-9474

    ER -