Abstract
The authors describe a new approach to custom LSI layout. This approach, called custom cell array, has a big advantage over conventional custom design approaches, incorporating custom cell array generator, automatic or interactive layout programs and a chip image optimizer. Several experimental results are shown, indicating the effectiveness of the approach. A 12% reduction in layout area size is achieved, compared with a conventional poly cell layout approach, and a 29-62% reduction is achieved, compared with the gate array approach.
| Original language | English |
|---|---|
| Pages (from-to) | 395-398 |
| Number of pages | 4 |
| Journal | Unknown Journal |
| Publication status | Published - 1985 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
Cite this
CUSTOM CELL ARRAY APPROACH TO VLSI LAYOUT. / Kitajima, F.; Takamizawa, K.; Nakamura, H.; Sugiyama, N.; Goto, S.
In: Unknown Journal, 1985, p. 395-398.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - CUSTOM CELL ARRAY APPROACH TO VLSI LAYOUT.
AU - Kitajima, F.
AU - Takamizawa, K.
AU - Nakamura, H.
AU - Sugiyama, N.
AU - Goto, S.
PY - 1985
Y1 - 1985
N2 - The authors describe a new approach to custom LSI layout. This approach, called custom cell array, has a big advantage over conventional custom design approaches, incorporating custom cell array generator, automatic or interactive layout programs and a chip image optimizer. Several experimental results are shown, indicating the effectiveness of the approach. A 12% reduction in layout area size is achieved, compared with a conventional poly cell layout approach, and a 29-62% reduction is achieved, compared with the gate array approach.
AB - The authors describe a new approach to custom LSI layout. This approach, called custom cell array, has a big advantage over conventional custom design approaches, incorporating custom cell array generator, automatic or interactive layout programs and a chip image optimizer. Several experimental results are shown, indicating the effectiveness of the approach. A 12% reduction in layout area size is achieved, compared with a conventional poly cell layout approach, and a 29-62% reduction is achieved, compared with the gate array approach.
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UR - http://www.scopus.com/inward/citedby.url?scp=0022307080&partnerID=8YFLogxK
M3 - Article
SP - 395
EP - 398
JO - Nuclear Physics A
JF - Nuclear Physics A
SN - 0375-9474
ER -