Delay-driven layer assignment in global routing under multi-tier interconnect structure

Jianchang Ao*, Sheqin Dong, Song Chen, Satoshi Goto

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Citations (Scopus)


A multilayer routing system usually adopts multiple interconnect configuration with different wire sizes and thicknesses. Since thicker layers of metal lead to fatter wires with smaller resistance, the layer assignment of nets has a large impact on the interconnect delay. However, such layer dependent characteristics have been ignored by most of the state-of-the-art academic layer assignment methods. To remedy this deficiency, this work studies a more effective layer assignment problem under such multi-tier interconnect structure, which arises during 3D global routing and focuses on minimizing both delays and via count. This work presents a two-stage algorithm to solve the problem, which first minimizes the total delay and via count simultaneously by dynamic programming and negotiation technique, and then further minimizes the maximum delay carefully while not increasing the via count. The experimental results on ICCAD09 benchmarks show that the proposed algorithm can significantly reduce the total delay and maximum delay while still keeping roughly the same via count, compared with the state-of-the-art via count minimization layer assignment method NVM.

Original languageEnglish
Title of host publicationProceedings of the International Symposium on Physical Design
Number of pages7
Publication statusPublished - 2013 Mar 24
Event2013 ACM International Symposium on Physical Design, ISPD 2013 - Stateline, NV
Duration: 2013 Mar 242013 Mar 27


Other2013 ACM International Symposium on Physical Design, ISPD 2013
CityStateline, NV


  • Delay optimization
  • Global routing
  • Layer assignment
  • Multi-tier interconnect structure
  • Via minimization

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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