TY - GEN
T1 - Density Aware Cell Library Design for Design-Technology Co-Optimization
AU - Nishizawa, Shinichi
AU - Nakura, Toru
N1 - Funding Information:
Acknowledgment This work was supported by JSPS KAKENHI Grant Numbers JP16K05382 and JP19H05608.
Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - This paper proposes a model to estimate the best layout style to maximize its power performance and area. Diffusion jogging is widely used to reduce its gate capacitance however sparse layout sometimes requires more area to improve layer density. Standard cell libraries with various layout styles were designed in commercial 65-nm process and evaluated its energy consumption and area considering its density constraint. Density aware library achieves 19% area reduction at the cost of 1.9% energy overhead.
AB - This paper proposes a model to estimate the best layout style to maximize its power performance and area. Diffusion jogging is widely used to reduce its gate capacitance however sparse layout sometimes requires more area to improve layer density. Standard cell libraries with various layout styles were designed in commercial 65-nm process and evaluated its energy consumption and area considering its density constraint. Density aware library achieves 19% area reduction at the cost of 1.9% energy overhead.
UR - http://www.scopus.com/inward/record.url?scp=85133751268&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85133751268&partnerID=8YFLogxK
U2 - 10.1109/ISQED54688.2022.9806236
DO - 10.1109/ISQED54688.2022.9806236
M3 - Conference contribution
AN - SCOPUS:85133751268
T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED
BT - Proceedings of the 23rd International Symposium on Quality Electronic Design, ISQED 2022
PB - IEEE Computer Society
T2 - 23rd International Symposium on Quality Electronic Design, ISQED 2022
Y2 - 6 April 2022 through 7 April 2022
ER -