DESCRIPTION AND VERIFICATION OF INPUT CONSTRAINTS AND INPUT-OUTPUT SPECIFICATIONS OF LOGIC CIRCUITS.

Shinji Kimura, Shuzo Yajima

Research output: Contribution to journalArticle

Abstract

The time is considered as discrete with sufficiently small steps, and the input and output of the logic circuit are treated as sequences. The method to describe the set of sequences satisfying the input constraints or the input-output specifications and the method to verify these assertions are proposed anew; # expression and the first # form are proposed as the description methods. The # expression is obtained by adding the newly proposed # concatenation and # closure to the regular expression. The first # form is a restricted # expression, where the number of states of the deterministic finite automaton accepting the set of sequences represented by the expression does not exceed twice the length of the description. In this paper, the logic circuit is regarded as a converter for the set of sequences and the verification of the input constraint or the input-output specification is reduced to the examination of the inclusive relation among the sets of sequences.

Original languageEnglish
Pages (from-to)29-42
Number of pages14
JournalSystems and Computers in Japan
Volume18
Issue number2
Publication statusPublished - 1987 Feb
Externally publishedYes

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Input Constraints
Logic circuits
Logic
Specification
Specifications
Output
Finite automata
Deterministic Finite Automata
Regular Expressions
Concatenation
Assertion
Converter
Exceed
Closure
Verify

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Hardware and Architecture
  • Information Systems
  • Theoretical Computer Science

Cite this

DESCRIPTION AND VERIFICATION OF INPUT CONSTRAINTS AND INPUT-OUTPUT SPECIFICATIONS OF LOGIC CIRCUITS. / Kimura, Shinji; Yajima, Shuzo.

In: Systems and Computers in Japan, Vol. 18, No. 2, 02.1987, p. 29-42.

Research output: Contribution to journalArticle

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