Design and implementation of an EOS chip

Liangwei Ge, Takeshi Yoshimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

As a very successful technology, Ethernet has now dominated the data transmission in LAN. However, some inborn defects, like the lack of guaranteed Quality of Services (QoS), restricts the maximum scope of Ethernet. Utilizing SDH/SONET, a technology for transmitting data over long distance, to overcome such limit is one promising solution. This solution termed Ethernet over SDH/SONET (EOS) combines the simplicity and affordability of Ethernet with the reliability and scalability of SDH/SONET. In this paper, the design and implementation of an EOS chip, which maps Ethernet fames into SONET/SDH payloads using both standard concatenation and virtual concatenation, is put forward. Several problems encountered during the implementation and their solutions are also discussed. The validity of the design has been proved by thorough functional simulation and FPGA verification.

Original languageEnglish
Title of host publicationASICON 2005: 2005 6th International Conference on ASIC, Proceedings
Pages350-353
Number of pages4
Volume1
Publication statusPublished - 2005
EventASICON 2005: 2005 6th International Conference on ASIC - Shanghai
Duration: 2005 Oct 242005 Oct 27

Other

OtherASICON 2005: 2005 6th International Conference on ASIC
CityShanghai
Period05/10/2405/10/27

Fingerprint

Ethernet
Local area networks
Data communication systems
Field programmable gate arrays (FPGA)
Scalability
Quality of service
Defects

Keywords

  • EOS
  • Flow control
  • SDH/SONET
  • Virtual concatenation

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Ge, L., & Yoshimura, T. (2005). Design and implementation of an EOS chip. In ASICON 2005: 2005 6th International Conference on ASIC, Proceedings (Vol. 1, pp. 350-353). [1611322]

Design and implementation of an EOS chip. / Ge, Liangwei; Yoshimura, Takeshi.

ASICON 2005: 2005 6th International Conference on ASIC, Proceedings. Vol. 1 2005. p. 350-353 1611322.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ge, L & Yoshimura, T 2005, Design and implementation of an EOS chip. in ASICON 2005: 2005 6th International Conference on ASIC, Proceedings. vol. 1, 1611322, pp. 350-353, ASICON 2005: 2005 6th International Conference on ASIC, Shanghai, 05/10/24.
Ge L, Yoshimura T. Design and implementation of an EOS chip. In ASICON 2005: 2005 6th International Conference on ASIC, Proceedings. Vol. 1. 2005. p. 350-353. 1611322
Ge, Liangwei ; Yoshimura, Takeshi. / Design and implementation of an EOS chip. ASICON 2005: 2005 6th International Conference on ASIC, Proceedings. Vol. 1 2005. pp. 350-353
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