Design and implementation of an EOS chip

Liangwei Ge*, Takeshi Yoshimura

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)


As a very successful technology, Ethernet has now dominated the data transmission in LAN. However, some inborn defects, like the lack of guaranteed Quality of Services (QoS), restricts the maximum scope of Ethernet. Utilizing SDH/SONET, a technology for transmitting data over long distance, to overcome such limit is one promising solution. This solution termed Ethernet over SDH/SONET (EOS) combines the simplicity and affordability of Ethernet with the reliability and scalability of SDH/SONET. In this paper, the design and implementation of an EOS chip, which maps Ethernet fames into SONET/SDH payloads using both standard concatenation and virtual concatenation, is put forward. Several problems encountered during the implementation and their solutions are also discussed. The validity of the design has been proved by thorough functional simulation and FPGA verification.

Original languageEnglish
Title of host publicationASICON 2005: 2005 6th International Conference on ASIC, Proceedings
Number of pages4
Publication statusPublished - 2005
EventASICON 2005: 2005 6th International Conference on ASIC - Shanghai
Duration: 2005 Oct 242005 Oct 27


OtherASICON 2005: 2005 6th International Conference on ASIC


  • EOS
  • Flow control
  • Virtual concatenation

ASJC Scopus subject areas

  • Engineering(all)


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