DESIGN AND REALIZATION OF AN LSI PROCESSOR FOR DIGITAL SIGNAL PROCESSING.

Kazuo Murano, Shigeyuki Unagami, Toshitaka Tsuda

    Research output: Contribution to journalArticle

    Abstract

    This paper describes a high-speed data processing LSI unit tailored to be used for digital signal processing (DSP) applications in the field of electrical communications. Also included in this paper are the results of its successful application to the 4800-bit/sec modem. The LSI processor discussed adopts a firmware control scheme to enhance flexibility and freedom of application. Further, it extensively utilizes the pipeline processing technique to attain highh-speed data handling capability. It handles 8-bit data at a clock frequency of up to 1. 152 MHz and performs about 144 K operations per second. The LSI chip contains 1500 gates and is packaged in a 40-pin DIP.

    Original languageEnglish
    Pages (from-to)39-53
    Number of pages15
    JournalFujitsu Sci Tech J
    Volume15
    Issue number1
    Publication statusPublished - 1979

    Fingerprint

    Digital signal processing
    Firmware
    Data handling
    Modems
    Clocks
    Pipelines
    Communication
    Processing

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Murano, K., Unagami, S., & Tsuda, T. (1979). DESIGN AND REALIZATION OF AN LSI PROCESSOR FOR DIGITAL SIGNAL PROCESSING. Fujitsu Sci Tech J, 15(1), 39-53.

    DESIGN AND REALIZATION OF AN LSI PROCESSOR FOR DIGITAL SIGNAL PROCESSING. / Murano, Kazuo; Unagami, Shigeyuki; Tsuda, Toshitaka.

    In: Fujitsu Sci Tech J, Vol. 15, No. 1, 1979, p. 39-53.

    Research output: Contribution to journalArticle

    Murano, K, Unagami, S & Tsuda, T 1979, 'DESIGN AND REALIZATION OF AN LSI PROCESSOR FOR DIGITAL SIGNAL PROCESSING.', Fujitsu Sci Tech J, vol. 15, no. 1, pp. 39-53.
    Murano, Kazuo ; Unagami, Shigeyuki ; Tsuda, Toshitaka. / DESIGN AND REALIZATION OF AN LSI PROCESSOR FOR DIGITAL SIGNAL PROCESSING. In: Fujitsu Sci Tech J. 1979 ; Vol. 15, No. 1. pp. 39-53.
    @article{f834ddbd0ab4408489f3b74776425eeb,
    title = "DESIGN AND REALIZATION OF AN LSI PROCESSOR FOR DIGITAL SIGNAL PROCESSING.",
    abstract = "This paper describes a high-speed data processing LSI unit tailored to be used for digital signal processing (DSP) applications in the field of electrical communications. Also included in this paper are the results of its successful application to the 4800-bit/sec modem. The LSI processor discussed adopts a firmware control scheme to enhance flexibility and freedom of application. Further, it extensively utilizes the pipeline processing technique to attain highh-speed data handling capability. It handles 8-bit data at a clock frequency of up to 1. 152 MHz and performs about 144 K operations per second. The LSI chip contains 1500 gates and is packaged in a 40-pin DIP.",
    author = "Kazuo Murano and Shigeyuki Unagami and Toshitaka Tsuda",
    year = "1979",
    language = "English",
    volume = "15",
    pages = "39--53",
    journal = "Fujitsu Scientific and Technical Journal",
    issn = "0016-2523",
    publisher = "Fujitsu Ltd",
    number = "1",

    }

    TY - JOUR

    T1 - DESIGN AND REALIZATION OF AN LSI PROCESSOR FOR DIGITAL SIGNAL PROCESSING.

    AU - Murano, Kazuo

    AU - Unagami, Shigeyuki

    AU - Tsuda, Toshitaka

    PY - 1979

    Y1 - 1979

    N2 - This paper describes a high-speed data processing LSI unit tailored to be used for digital signal processing (DSP) applications in the field of electrical communications. Also included in this paper are the results of its successful application to the 4800-bit/sec modem. The LSI processor discussed adopts a firmware control scheme to enhance flexibility and freedom of application. Further, it extensively utilizes the pipeline processing technique to attain highh-speed data handling capability. It handles 8-bit data at a clock frequency of up to 1. 152 MHz and performs about 144 K operations per second. The LSI chip contains 1500 gates and is packaged in a 40-pin DIP.

    AB - This paper describes a high-speed data processing LSI unit tailored to be used for digital signal processing (DSP) applications in the field of electrical communications. Also included in this paper are the results of its successful application to the 4800-bit/sec modem. The LSI processor discussed adopts a firmware control scheme to enhance flexibility and freedom of application. Further, it extensively utilizes the pipeline processing technique to attain highh-speed data handling capability. It handles 8-bit data at a clock frequency of up to 1. 152 MHz and performs about 144 K operations per second. The LSI chip contains 1500 gates and is packaged in a 40-pin DIP.

    UR - http://www.scopus.com/inward/record.url?scp=0018321495&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=0018321495&partnerID=8YFLogxK

    M3 - Article

    AN - SCOPUS:0018321495

    VL - 15

    SP - 39

    EP - 53

    JO - Fujitsu Scientific and Technical Journal

    JF - Fujitsu Scientific and Technical Journal

    SN - 0016-2523

    IS - 1

    ER -