Design-for-secure-test for crypto cores

Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki

doi:10.1109/TEST.2009.5355900

Design-for-secure-test for crypto cores

Youhua Shi^*, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

^*Corresponding author for this work

School of Fundamental Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

Scan technology carries the potential of being misused as a "side channel" to leak out the secret information of crypto cores. To address such a design challenge, this paper proposes a design-for-secure-test (DFST) solution for crypto cores by adding a stimuli-launched flip-flop into the traditional scan flip-flop to maintain the high test quality without compromising the security.

Original language	English
Title of host publication	International Test Conference, ITC 2009 - Proceedings
DOIs	https://doi.org/10.1109/TEST.2009.5355900
Publication status	Published - 2009 Dec 15
Event	International Test Conference, ITC 2009 - Austin, TX, United States Duration: 2009 Nov 1 → 2009 Nov 6

Publication series

Name	Proceedings - International Test Conference
ISSN (Print)	1089-3539

Conference

Conference	International Test Conference, ITC 2009
Country/Territory	United States
City	Austin, TX
Period	09/11/1 → 09/11/6

ASJC Scopus subject areas

Electrical and Electronic Engineering
Applied Mathematics

Access to Document

10.1109/TEST.2009.5355900

Cite this

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abstract = "Scan technology carries the potential of being misused as a {"}side channel{"} to leak out the secret information of crypto cores. To address such a design challenge, this paper proposes a design-for-secure-test (DFST) solution for crypto cores by adding a stimuli-launched flip-flop into the traditional scan flip-flop to maintain the high test quality without compromising the security.",

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AU - Shi, Youhua

AU - Togawa, Nozomu

AU - Yanagisawa, Masao

AU - Ohtsuki, Tatsuo

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Y1 - 2009/12/15

N2 - Scan technology carries the potential of being misused as a "side channel" to leak out the secret information of crypto cores. To address such a design challenge, this paper proposes a design-for-secure-test (DFST) solution for crypto cores by adding a stimuli-launched flip-flop into the traditional scan flip-flop to maintain the high test quality without compromising the security.

AB - Scan technology carries the potential of being misused as a "side channel" to leak out the secret information of crypto cores. To address such a design challenge, this paper proposes a design-for-secure-test (DFST) solution for crypto cores by adding a stimuli-launched flip-flop into the traditional scan flip-flop to maintain the high test quality without compromising the security.

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M3 - Conference contribution

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Design-for-secure-test for crypto cores

Abstract

Publication series

Conference

ASJC Scopus subject areas

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