Design-for-secure-test for crypto cores

Youhua Shi*, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)


Scan technology carries the potential of being misused as a "side channel" to leak out the secret information of crypto cores. To address such a design challenge, this paper proposes a design-for-secure-test (DFST) solution for crypto cores by adding a stimuli-launched flip-flop into the traditional scan flip-flop to maintain the high test quality without compromising the security.

Original languageEnglish
Title of host publicationInternational Test Conference, ITC 2009 - Proceedings
Publication statusPublished - 2009 Dec 15
EventInternational Test Conference, ITC 2009 - Austin, TX, United States
Duration: 2009 Nov 12009 Nov 6

Publication series

NameProceedings - International Test Conference
ISSN (Print)1089-3539


ConferenceInternational Test Conference, ITC 2009
Country/TerritoryUnited States
CityAustin, TX

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Applied Mathematics


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