Design methodology for variation tolerant d-flip-flop using regression analysis

Shinichi Nishizawa, Hidetoshi Onodera

Research output: Contribution to journalArticlepeer-review

Abstract

This paper describes a design methodology for process variation aware D-Flip-Flop (DFF) using regression analysis. We propose to use a regression analysis to model the worst-case delay characteristics of a DFF under process variation. We utilize the regression equation for transistor width tuning of the DFF to improve its worst-case delay performance. Regression analysis can not only identify the performance-critical transistors inside the DFF, but also shows these impacts on DFF delay performance in quantitative form. Proposed design methodology is verified using Monte-Carlo simulation. The result shows the proposed method achieves to design a DFF which has similar or better delay characteristics in comparison with the DFF designed by an experienced cell designer.

Original languageEnglish
Pages (from-to)2222-2230
Number of pages9
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE101A
Issue number12
DOIs
Publication statusPublished - 2018 Dec
Externally publishedYes

Keywords

  • D-Flip-Flop
  • Regression analysis
  • Variation aware design

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

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