Design methodology of a robust bsd protection circuit for sti process 256 mb nand flash memory

Tamio Ikehashi, Kenichi Imamiya, Koji Sakui

Research output: Contribution to journalArticle

Abstract

With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n- junction with n+ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness.

Original languageEnglish
Pages (from-to)246-254
Number of pages9
JournalIEEE Transactions on Electronics Packaging Manufacturing
Volume23
Issue number4
DOIs
Publication statusPublished - 2000 Dec 1
Externally publishedYes

Fingerprint

Flash memory
Simulators
Networks (circuits)

Keywords

  • Contact hole diffusion
  • Device simulation
  • Drain spacing
  • ESD
  • HBM
  • Lateral npn bipolar protection
  • MM
  • Nonsilicided junction
  • STI

ASJC Scopus subject areas

  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering

Cite this

Design methodology of a robust bsd protection circuit for sti process 256 mb nand flash memory. / Ikehashi, Tamio; Imamiya, Kenichi; Sakui, Koji.

In: IEEE Transactions on Electronics Packaging Manufacturing, Vol. 23, No. 4, 01.12.2000, p. 246-254.

Research output: Contribution to journalArticle

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