Design methodology of a robust esd protection circuit for sti process 256 mb nand flash memory

Tamio Ikehashi, Kenichi Imamiya, Koji Sakui

Research output: Contribution to journalArticle

Abstract

With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n junction with n+ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness.

Original languageEnglish
Number of pages1
JournalIEEE Transactions on Electronics Packaging Manufacturing
Volume23
Issue number4
DOIs
Publication statusPublished - 2000 Jan 1
Externally publishedYes

Fingerprint

Flash memory
Simulators
Networks (circuits)

ASJC Scopus subject areas

  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering

Cite this

Design methodology of a robust esd protection circuit for sti process 256 mb nand flash memory. / Ikehashi, Tamio; Imamiya, Kenichi; Sakui, Koji.

In: IEEE Transactions on Electronics Packaging Manufacturing, Vol. 23, No. 4, 01.01.2000.

Research output: Contribution to journalArticle

@article{c29f96bcdbf84b8db430859fe7bc56cb,
title = "Design methodology of a robust esd protection circuit for sti process 256 mb nand flash memory",
abstract = "With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n junction with n+ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness.",
author = "Tamio Ikehashi and Kenichi Imamiya and Koji Sakui",
year = "2000",
month = "1",
day = "1",
doi = "10.1109/TEPM.2000.895053",
language = "English",
volume = "23",
journal = "IEEE Transactions on Electronics Packaging Manufacturing",
issn = "1521-334X",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "4",

}

TY - JOUR

T1 - Design methodology of a robust esd protection circuit for sti process 256 mb nand flash memory

AU - Ikehashi, Tamio

AU - Imamiya, Kenichi

AU - Sakui, Koji

PY - 2000/1/1

Y1 - 2000/1/1

N2 - With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n junction with n+ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness.

AB - With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n junction with n+ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness.

UR - http://www.scopus.com/inward/record.url?scp=33747987735&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33747987735&partnerID=8YFLogxK

U2 - 10.1109/TEPM.2000.895053

DO - 10.1109/TEPM.2000.895053

M3 - Article

AN - SCOPUS:33747987735

VL - 23

JO - IEEE Transactions on Electronics Packaging Manufacturing

JF - IEEE Transactions on Electronics Packaging Manufacturing

SN - 1521-334X

IS - 4

ER -