Design methodology of a robust esd protection circuit for sti process 256 mb nand flash memory

Tamio Ikehashi; Kenichi Imamiya; Koji Sakui

doi:10.1109/TEPM.2000.895053

Design methodology of a robust esd protection circuit for sti process 256 mb nand flash memory

Tamio Ikehashi^*, Kenichi Imamiya, Koji Sakui

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

Abstract

With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n junction with n⁺ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness.

Original language	English
Pages (from-to)	235
Number of pages	1
Journal	IEEE Transactions on Electronics Packaging Manufacturing
Volume	23
Issue number	4
DOIs	https://doi.org/10.1109/TEPM.2000.895053
Publication status	Published - 2000
Externally published	Yes

ASJC Scopus subject areas

Industrial and Manufacturing Engineering
Electrical and Electronic Engineering

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10.1109/TEPM.2000.895053

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title = "Design methodology of a robust esd protection circuit for sti process 256 mb nand flash memory",

abstract = "With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n junction with n+ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness.",

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AU - Sakui, Koji

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N2 - With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n junction with n+ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness.

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Design methodology of a robust esd protection circuit for sti process 256 mb nand flash memory

Abstract

ASJC Scopus subject areas

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