Design methodology of a robust esd protection circuit for sti process 256 mb nand flash memory

Tamio Ikehashi, Kenichi Imamiya, Koji Sakui

Research output: Contribution to journalArticle

Abstract

With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n junction with n+ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness.

Original languageEnglish
Number of pages1
JournalIEEE Transactions on Electronics Packaging Manufacturing
Volume23
Issue number4
DOIs
Publication statusPublished - 2000 Jan 1
Externally publishedYes

    Fingerprint

ASJC Scopus subject areas

  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering

Cite this