Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory

Tamio Ikehashi, Kenichi Imamiya, Koji Sakui

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

With the use of a device simulator, it is shown that an electrostatic discharge (ESD) protection circuit whose junction filled with contacts is suited to a scaled shallow trench isolation (STI) process having thin n- junction with n+ being implanted from contact holes. It is confirmed by measurements that the protection has sufficient robustness.

Original languageEnglish
Title of host publicationElectrical Overstress/Electrostatic Discharge Symposium Proceedings
PublisherESD Assoc
Pages225-234
Number of pages10
ISBN (Print)158537007X
Publication statusPublished - 1999 Dec 1
Externally publishedYes
EventProceedings of the 1999 EOS/ESD Symposium 'Electrical Overstress/Electrostatic Discharge' - Orlando, FL, USA
Duration: 1999 Sep 281999 Sep 30

Publication series

NameElectrical Overstress/Electrostatic Discharge Symposium Proceedings
ISSN (Print)0739-5159

Conference

ConferenceProceedings of the 1999 EOS/ESD Symposium 'Electrical Overstress/Electrostatic Discharge'
CityOrlando, FL, USA
Period99/9/2899/9/30

Fingerprint

circuit protection
flash
isolation
methodology
electrostatics
simulators
electric contacts

ASJC Scopus subject areas

  • Condensed Matter Physics

Cite this

Ikehashi, T., Imamiya, K., & Sakui, K. (1999). Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory. In Electrical Overstress/Electrostatic Discharge Symposium Proceedings (pp. 225-234). (Electrical Overstress/Electrostatic Discharge Symposium Proceedings). ESD Assoc.

Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory. / Ikehashi, Tamio; Imamiya, Kenichi; Sakui, Koji.

Electrical Overstress/Electrostatic Discharge Symposium Proceedings. ESD Assoc, 1999. p. 225-234 (Electrical Overstress/Electrostatic Discharge Symposium Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ikehashi, T, Imamiya, K & Sakui, K 1999, Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory. in Electrical Overstress/Electrostatic Discharge Symposium Proceedings. Electrical Overstress/Electrostatic Discharge Symposium Proceedings, ESD Assoc, pp. 225-234, Proceedings of the 1999 EOS/ESD Symposium 'Electrical Overstress/Electrostatic Discharge', Orlando, FL, USA, 99/9/28.
Ikehashi T, Imamiya K, Sakui K. Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory. In Electrical Overstress/Electrostatic Discharge Symposium Proceedings. ESD Assoc. 1999. p. 225-234. (Electrical Overstress/Electrostatic Discharge Symposium Proceedings).
Ikehashi, Tamio ; Imamiya, Kenichi ; Sakui, Koji. / Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory. Electrical Overstress/Electrostatic Discharge Symposium Proceedings. ESD Assoc, 1999. pp. 225-234 (Electrical Overstress/Electrostatic Discharge Symposium Proceedings).
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