Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory

Tamio Ikehashi; Kenichi Imamiya; Koji Sakui

Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory

Tamio Ikehashi^*, Kenichi Imamiya, Koji Sakui

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

With the use of a device simulator, it is shown that an electrostatic discharge (ESD) protection circuit whose junction filled with contacts is suited to a scaled shallow trench isolation (STI) process having thin n^- junction with n⁺ being implanted from contact holes. It is confirmed by measurements that the protection has sufficient robustness.

Original language	English
Title of host publication	Electrical Overstress/Electrostatic Discharge Symposium Proceedings
Publisher	ESD Assoc
Pages	225-234
Number of pages	10
ISBN (Print)	158537007X
Publication status	Published - 1999 Dec 1
Externally published	Yes
Event	Proceedings of the 1999 EOS/ESD Symposium 'Electrical Overstress/Electrostatic Discharge' - Orlando, FL, USA Duration: 1999 Sept 28 → 1999 Sept 30

Publication series

Name	Electrical Overstress/Electrostatic Discharge Symposium Proceedings
ISSN (Print)	0739-5159

Conference

Conference	Proceedings of the 1999 EOS/ESD Symposium 'Electrical Overstress/Electrostatic Discharge'
City	Orlando, FL, USA
Period	99/9/28 → 99/9/30

ASJC Scopus subject areas

Condensed Matter Physics

Cite this

Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory. / Ikehashi, Tamio; Imamiya, Kenichi; Sakui, Koji.

Electrical Overstress/Electrostatic Discharge Symposium Proceedings. ESD Assoc, 1999. p. 225-234 (Electrical Overstress/Electrostatic Discharge Symposium Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ikehashi, T, Imamiya, K & Sakui, K 1999, Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory. in Electrical Overstress/Electrostatic Discharge Symposium Proceedings. Electrical Overstress/Electrostatic Discharge Symposium Proceedings, ESD Assoc, pp. 225-234, Proceedings of the 1999 EOS/ESD Symposium 'Electrical Overstress/Electrostatic Discharge', Orlando, FL, USA, 99/9/28.

@inproceedings{d14f3b31e92b408586364bd5baebd9dd,

title = "Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory",

abstract = "With the use of a device simulator, it is shown that an electrostatic discharge (ESD) protection circuit whose junction filled with contacts is suited to a scaled shallow trench isolation (STI) process having thin n- junction with n+ being implanted from contact holes. It is confirmed by measurements that the protection has sufficient robustness.",

author = "Tamio Ikehashi and Kenichi Imamiya and Koji Sakui",

year = "1999",

month = dec,

day = "1",

language = "English",

isbn = "158537007X",

series = "Electrical Overstress/Electrostatic Discharge Symposium Proceedings",

publisher = "ESD Assoc",

pages = "225--234",

booktitle = "Electrical Overstress/Electrostatic Discharge Symposium Proceedings",

note = "Proceedings of the 1999 EOS/ESD Symposium 'Electrical Overstress/Electrostatic Discharge' ; Conference date: 28-09-1999 Through 30-09-1999",

}

TY - GEN

T1 - Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory

AU - Ikehashi, Tamio

AU - Imamiya, Kenichi

AU - Sakui, Koji

PY - 1999/12/1

Y1 - 1999/12/1

N2 - With the use of a device simulator, it is shown that an electrostatic discharge (ESD) protection circuit whose junction filled with contacts is suited to a scaled shallow trench isolation (STI) process having thin n- junction with n+ being implanted from contact holes. It is confirmed by measurements that the protection has sufficient robustness.

AB - With the use of a device simulator, it is shown that an electrostatic discharge (ESD) protection circuit whose junction filled with contacts is suited to a scaled shallow trench isolation (STI) process having thin n- junction with n+ being implanted from contact holes. It is confirmed by measurements that the protection has sufficient robustness.

UR - http://www.scopus.com/inward/record.url?scp=0033279726&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033279726&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0033279726

SN - 158537007X

T3 - Electrical Overstress/Electrostatic Discharge Symposium Proceedings

SP - 225

EP - 234

BT - Electrical Overstress/Electrostatic Discharge Symposium Proceedings

PB - ESD Assoc

T2 - Proceedings of the 1999 EOS/ESD Symposium 'Electrical Overstress/Electrostatic Discharge'

Y2 - 28 September 1999 through 30 September 1999

ER -

Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory

Abstract

Publication series

Conference

ASJC Scopus subject areas

Other files and links

Fingerprint

Cite this