Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation

Shinichi Nishizawa*, Tohru Ishihara, Hidetoshi Onodera

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper describes the process variation tolerant design of DFFs for low voltage operation. Within-die random variation have a strong impact on the delay performance of DFF, especially at low supply voltage. Since a large number of DFFs are used in a VLSI chip, operation failure or timing failure of DFFs cause operation failure of a VLSI chip. This paper analyzes operation failures of DFFs using Monte-Carlo analysis and evaluate the effect of within-die variation on the delay performance of DFFs. In order to mitigate the effect of within-die variation, variation tolerant DFF design is proposed. The post layout simulation result shows increasing the sizes of the input clocked inverter and the clock driver reduce the operational failure of DFFs.

Original languageEnglish
Title of host publicationInternational System on Chip Conference
EditorsRamalingam Sridhar, Danella Zhao, Kaijian Shi, Thomas Buchner
PublisherIEEE Computer Society
Pages42-47
Number of pages6
ISBN (Electronic)9781479933785
DOIs
Publication statusPublished - 2014 Nov 5
Externally publishedYes
Event27th IEEE International System on Chip Conference, SOCC 2014 - Las Vegas, United States
Duration: 2014 Sep 22014 Sep 5

Publication series

NameInternational System on Chip Conference
ISSN (Print)2164-1676
ISSN (Electronic)2164-1706

Conference

Conference27th IEEE International System on Chip Conference, SOCC 2014
Country/TerritoryUnited States
CityLas Vegas
Period14/9/214/9/5

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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