Design of a 128-mb SOI DRAM using the floating body cell (FBC)

Takashi Ohsawa, K. Fujita, K. Hatsuda, T. Higashi, T. Shino, Y. Minami, H. Nakajima, M. Morikado, K. Inoh, T. Hamamoto, S. Watanabe, S. Fujii, T. Furuyama

Research output: Contribution to journalArticle

10 Citations (Scopus)

Abstract

A 128-Mb SOI DRAM has been developed featuring the floating body cell (FBC). To keep the cell data state from being degraded by the word-line (WL) disturb due to the charge pumping and to reduce the refresh busy rate, a sense amplifier (S/A) is arranged for every bit-line (BL) and replenishes data "1" cells' bodies with holes which are lost by the disturb in every read and write cycle. The power is reduced by operating the S/As asymmetrically between the selected and the unselected thanks to that the number of holes to be replenished in the unselected S/As for charge pumping is two order of magnitude smaller than that required for writing the data "1". The multi-pair averaging of dummy cells generates a very accurate reference current for distinguishing the data "1" and "0" and a Monte Carlo simulation shows that it achieves a sensing scheme robust enough to realize all good parts of the DRAM with a reasonable amount of redundancy. The cell's feature of quasi-nondestructive read-out is also advantageous for making an SRAM interface of the DRAM or hiding refresh from uses without sacrificing the access time.

Original languageEnglish
Pages (from-to)135-145
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume41
Issue number1
DOIs
Publication statusPublished - 2006 Jan
Externally publishedYes

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Dynamic random access storage
Static random access storage
Redundancy

Keywords

  • 128 Mbit
  • Charge pumping
  • DRAM robustness
  • Dummy cells
  • Floating body cell
  • Monte Carlo simulation
  • Multi-pair averaging
  • Quasi-nondestructive read-out
  • Redundancy
  • Sense amplifier
  • Silicon-on-insulator technology
  • SOI DRAM
  • Word-line disturb

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Ohsawa, T., Fujita, K., Hatsuda, K., Higashi, T., Shino, T., Minami, Y., ... Furuyama, T. (2006). Design of a 128-mb SOI DRAM using the floating body cell (FBC). IEEE Journal of Solid-State Circuits, 41(1), 135-145. https://doi.org/10.1109/JSSC.0051.859018

Design of a 128-mb SOI DRAM using the floating body cell (FBC). / Ohsawa, Takashi; Fujita, K.; Hatsuda, K.; Higashi, T.; Shino, T.; Minami, Y.; Nakajima, H.; Morikado, M.; Inoh, K.; Hamamoto, T.; Watanabe, S.; Fujii, S.; Furuyama, T.

In: IEEE Journal of Solid-State Circuits, Vol. 41, No. 1, 01.2006, p. 135-145.

Research output: Contribution to journalArticle

Ohsawa, T, Fujita, K, Hatsuda, K, Higashi, T, Shino, T, Minami, Y, Nakajima, H, Morikado, M, Inoh, K, Hamamoto, T, Watanabe, S, Fujii, S & Furuyama, T 2006, 'Design of a 128-mb SOI DRAM using the floating body cell (FBC)', IEEE Journal of Solid-State Circuits, vol. 41, no. 1, pp. 135-145. https://doi.org/10.1109/JSSC.0051.859018
Ohsawa, Takashi ; Fujita, K. ; Hatsuda, K. ; Higashi, T. ; Shino, T. ; Minami, Y. ; Nakajima, H. ; Morikado, M. ; Inoh, K. ; Hamamoto, T. ; Watanabe, S. ; Fujii, S. ; Furuyama, T. / Design of a 128-mb SOI DRAM using the floating body cell (FBC). In: IEEE Journal of Solid-State Circuits. 2006 ; Vol. 41, No. 1. pp. 135-145.
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