Abstract
Nowadays, security has become an important topic of interest to researchers. Different types of cryptography algorithms have been developed in order to improve the performance of these information-protecting procedures. A hash function is a cryptography algorithm without a key such as MD5, RIPEMD160, and SHA-1. In this paper, a new SHA family is developed and designed in order to fulfil the cryptographic algorithm performance requirement. Thus, SHA-256 design and SHA-256 unfolding design based on reconfigurable hardware have been successfully completed using Verilog code. These designs were simulated and verified using ModelSim. The results showed that the proposed SHA-256 unfolding design gave better performance on Arria II GX in terms of throughput. The high throughput of SHA-256 unfolding design was obtained at a data transfer speed of 2429.52 Mbps.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 2017 6th International Conference on Electrical Engineering and Informatics |
| Subtitle of host publication | Sustainable Society Through Digital Innovation, ICEEI 2017 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 1-6 |
| Number of pages | 6 |
| Volume | 2017-November |
| ISBN (Electronic) | 9781538604755 |
| DOIs | |
| Publication status | Published - 2018 Mar 9 |
| Event | 6th International Conference on Electrical Engineering and Informatics, ICEEI 2017 - Langkawi, Malaysia Duration: 2017 Nov 25 → 2017 Nov 27 |
Other
| Other | 6th International Conference on Electrical Engineering and Informatics, ICEEI 2017 |
|---|---|
| Country | Malaysia |
| City | Langkawi |
| Period | 17/11/25 → 17/11/27 |
Fingerprint
Keywords
- Cryptography algorithm
- FPGA
- SHA256 Hash Function
- Unfolding transformation
ASJC Scopus subject areas
- Artificial Intelligence
- Control and Optimization
- Computer Networks and Communications
- Computer Vision and Pattern Recognition
- Information Systems
- Software
- Electrical and Electronic Engineering
- Health Informatics
Cite this
Design of high-throughput SHA-256 hash function based on FPGA. / Binti Suhaili, Shamsiah; Watanabe, Takahiro.
Proceedings of the 2017 6th International Conference on Electrical Engineering and Informatics: Sustainable Society Through Digital Innovation, ICEEI 2017. Vol. 2017-November Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-6.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Design of high-throughput SHA-256 hash function based on FPGA
AU - Binti Suhaili, Shamsiah
AU - Watanabe, Takahiro
PY - 2018/3/9
Y1 - 2018/3/9
N2 - Nowadays, security has become an important topic of interest to researchers. Different types of cryptography algorithms have been developed in order to improve the performance of these information-protecting procedures. A hash function is a cryptography algorithm without a key such as MD5, RIPEMD160, and SHA-1. In this paper, a new SHA family is developed and designed in order to fulfil the cryptographic algorithm performance requirement. Thus, SHA-256 design and SHA-256 unfolding design based on reconfigurable hardware have been successfully completed using Verilog code. These designs were simulated and verified using ModelSim. The results showed that the proposed SHA-256 unfolding design gave better performance on Arria II GX in terms of throughput. The high throughput of SHA-256 unfolding design was obtained at a data transfer speed of 2429.52 Mbps.
AB - Nowadays, security has become an important topic of interest to researchers. Different types of cryptography algorithms have been developed in order to improve the performance of these information-protecting procedures. A hash function is a cryptography algorithm without a key such as MD5, RIPEMD160, and SHA-1. In this paper, a new SHA family is developed and designed in order to fulfil the cryptographic algorithm performance requirement. Thus, SHA-256 design and SHA-256 unfolding design based on reconfigurable hardware have been successfully completed using Verilog code. These designs were simulated and verified using ModelSim. The results showed that the proposed SHA-256 unfolding design gave better performance on Arria II GX in terms of throughput. The high throughput of SHA-256 unfolding design was obtained at a data transfer speed of 2429.52 Mbps.
KW - Cryptography algorithm
KW - FPGA
KW - SHA256 Hash Function
KW - Unfolding transformation
UR - http://www.scopus.com/inward/record.url?scp=85050798557&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85050798557&partnerID=8YFLogxK
U2 - 10.1109/ICEEI.2017.8312449
DO - 10.1109/ICEEI.2017.8312449
M3 - Conference contribution
AN - SCOPUS:85050798557
VL - 2017-November
SP - 1
EP - 6
BT - Proceedings of the 2017 6th International Conference on Electrical Engineering and Informatics
PB - Institute of Electrical and Electronics Engineers Inc.
ER -