TY - GEN
T1 - Design of high-throughput SHA-256 hash function based on FPGA
AU - Binti Suhaili, Shamsiah
AU - Watanabe, Takahiro
N1 - Funding Information:
This project is supported by Universiti Malaysia Sarawak (UNIMAS) under grant code L18403/F02/00/Osaka/Research
Publisher Copyright:
© 2017 IEEE.
PY - 2018/3/9
Y1 - 2018/3/9
N2 - Nowadays, security has become an important topic of interest to researchers. Different types of cryptography algorithms have been developed in order to improve the performance of these information-protecting procedures. A hash function is a cryptography algorithm without a key such as MD5, RIPEMD160, and SHA-1. In this paper, a new SHA family is developed and designed in order to fulfil the cryptographic algorithm performance requirement. Thus, SHA-256 design and SHA-256 unfolding design based on reconfigurable hardware have been successfully completed using Verilog code. These designs were simulated and verified using ModelSim. The results showed that the proposed SHA-256 unfolding design gave better performance on Arria II GX in terms of throughput. The high throughput of SHA-256 unfolding design was obtained at a data transfer speed of 2429.52 Mbps.
AB - Nowadays, security has become an important topic of interest to researchers. Different types of cryptography algorithms have been developed in order to improve the performance of these information-protecting procedures. A hash function is a cryptography algorithm without a key such as MD5, RIPEMD160, and SHA-1. In this paper, a new SHA family is developed and designed in order to fulfil the cryptographic algorithm performance requirement. Thus, SHA-256 design and SHA-256 unfolding design based on reconfigurable hardware have been successfully completed using Verilog code. These designs were simulated and verified using ModelSim. The results showed that the proposed SHA-256 unfolding design gave better performance on Arria II GX in terms of throughput. The high throughput of SHA-256 unfolding design was obtained at a data transfer speed of 2429.52 Mbps.
KW - Cryptography algorithm
KW - FPGA
KW - SHA256 Hash Function
KW - Unfolding transformation
UR - http://www.scopus.com/inward/record.url?scp=85050798557&partnerID=8YFLogxK
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U2 - 10.1109/ICEEI.2017.8312449
DO - 10.1109/ICEEI.2017.8312449
M3 - Conference contribution
AN - SCOPUS:85050798557
T3 - Proceedings of the 2017 6th International Conference on Electrical Engineering and Informatics: Sustainable Society Through Digital Innovation, ICEEI 2017
SP - 1
EP - 6
BT - Proceedings of the 2017 6th International Conference on Electrical Engineering and Informatics
A2 - Zin, Nor Azan Mat
A2 - Bakar, Marini Abu
A2 - Mohamad, Masnizah
A2 - Tiun, Sabrina
A2 - Abdullah, Huda
A2 - Mohamed, Hazura
A2 - Ahmad, Kamsuriah
A2 - Shukur, Zarina
A2 - Yusof, Zawiyah Mohamad
A2 - Mokhtar, Mohamad Hadri Hafiz
A2 - Jenal, Ruzzakiah
A2 - Judi, Hairulliza Mohamad
A2 - Bukhori, Muhammad Faiz
A2 - Mukhtar, Muriati
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 6th International Conference on Electrical Engineering and Informatics, ICEEI 2017
Y2 - 25 November 2017 through 27 November 2017
ER -