Design of Power and Area Efficient Lower-Part-OR Approximate Multiplier

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Approximate computing has been paid attention as a promising technique to decrease power and area for error-tolerant applications by simplifying the internal operations with sacrificing their accuracy. In this paper, a new power and area efficient approximate multiplier is proposed using OR based compressor with no carry propagation for lower bit positions and a carry propagation compressor with inexact half adders and full adders for upper bit positions. The proposal is effective to reduce the critical path delay with almost the same precision with previous methods. Firstly, an inexact half adder and an inexact full adder are proposed and a construction method of 4×4 multiplier is shown. Then, a construction method of 8×8 multiplier is proposed using OR based compressor, approximate 4×4 multipliers and an accurate 4×4 multiplier. The proposed construction method can also be applied to 16×16 multiplier. The accuracy loss of proposed multipliers is evaluated using MATLAB simulation and that of the proposed 8×8 multiplier is low as 0.20%, the effect of which is shown to be negligible by applying to discrete cosine transform (DCT), inverse DCT and convolutional neural networks for image classification. The proposed 8×8 multiplier reduces power and area by 50.78% and 53.19%, respectively, compared with the accurate Wallace tree multiplier when evaluated using SMIC 40nm process.

Original languageEnglish
Title of host publicationProceedings of TENCON 2018 - 2018 IEEE Region 10 Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages2110-2115
Number of pages6
ISBN (Electronic)9781538654576
DOIs
Publication statusPublished - 2019 Feb 22
Event2018 IEEE Region 10 Conference, TENCON 2018 - Jeju, Korea, Republic of
Duration: 2018 Oct 282018 Oct 31

Publication series

NameIEEE Region 10 Annual International Conference, Proceedings/TENCON
Volume2018-October
ISSN (Print)2159-3442
ISSN (Electronic)2159-3450

Conference

Conference2018 IEEE Region 10 Conference, TENCON 2018
CountryKorea, Republic of
CityJeju
Period18/10/2818/10/31

Fingerprint

Adders
Compressors
Discrete cosine transforms
Image classification
MATLAB
Neural networks

Keywords

  • approximate multiplier
  • high performance
  • OR gate
  • top-down construction

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

Cite this

Guo, Y., Sun, H., & Kimura, S. (2019). Design of Power and Area Efficient Lower-Part-OR Approximate Multiplier. In Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference (pp. 2110-2115). [8650108] (IEEE Region 10 Annual International Conference, Proceedings/TENCON; Vol. 2018-October). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/TENCON.2018.8650108

Design of Power and Area Efficient Lower-Part-OR Approximate Multiplier. / Guo, Yi; Sun, Heming; Kimura, Shinji.

Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference. Institute of Electrical and Electronics Engineers Inc., 2019. p. 2110-2115 8650108 (IEEE Region 10 Annual International Conference, Proceedings/TENCON; Vol. 2018-October).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Guo, Y, Sun, H & Kimura, S 2019, Design of Power and Area Efficient Lower-Part-OR Approximate Multiplier. in Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference., 8650108, IEEE Region 10 Annual International Conference, Proceedings/TENCON, vol. 2018-October, Institute of Electrical and Electronics Engineers Inc., pp. 2110-2115, 2018 IEEE Region 10 Conference, TENCON 2018, Jeju, Korea, Republic of, 18/10/28. https://doi.org/10.1109/TENCON.2018.8650108
Guo Y, Sun H, Kimura S. Design of Power and Area Efficient Lower-Part-OR Approximate Multiplier. In Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference. Institute of Electrical and Electronics Engineers Inc. 2019. p. 2110-2115. 8650108. (IEEE Region 10 Annual International Conference, Proceedings/TENCON). https://doi.org/10.1109/TENCON.2018.8650108
Guo, Yi ; Sun, Heming ; Kimura, Shinji. / Design of Power and Area Efficient Lower-Part-OR Approximate Multiplier. Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 2110-2115 (IEEE Region 10 Annual International Conference, Proceedings/TENCON).
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