Design of well-behaved low-loss millimetre-wave CMOS transmission lines

S. Amakawa, A. Orii, Kosuke Katayama, K. Takano, M. Motoyoshi, T. Yoshida, M. Fujishima

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Abstract

It is a challenge to design single-mode transmission lines for above 100 GHz following strict design rules of modern CMOS processes. This paper reports characteristics of three types of microstrip lines in 65 nm CMOS up to 325 GHz, designed with or without using an auto-dummy exclusion layer. The lowest-loss design among the three is a shielded microstrip protected with an exclusion layer. The metal density requirement is met, as is commonly done, by placing sidewalls as far from the signal line as allowed by the design rules. The other two designs are microstrips without sidewalls or the exclusion layer. One of them has high-density auto dummy fill inserted by the foundry and shows significantly higher attenuation than the shielded microstrip. The other is filled with low-density fill that prevents auto dummy fill from being inserted. It is only marginally lossier than the shielded microstrip. The microstrips without sidewalls are found to exhibit more well-behaved attenuation especially above 100 GHz. The frequency dependence of the attenuation of the shielded microstrip, on the other hand, exhibits ripples, indicating possible presence of spurious modes. Attenuation constants estimated by multiline TRL (thru-reflect-line) from lines of various lengths indicate that the longest line measured should be very long, perhaps 2mm or longer, for the estimates to be reliable.

Original languageEnglish
Title of host publication2014 18th IEEE Workshop on Signal and Power Integrity, SPI 2014 - Proceedings
PublisherIEEE Computer Society
ISBN (Print)9781479935994
DOIs
Publication statusPublished - 2014
Externally publishedYes
Event18th IEEE Workshop on Signal and Power Integrity, SPI 2014 - Ghent, Belgium
Duration: 2014 May 112014 May 14

Other

Other18th IEEE Workshop on Signal and Power Integrity, SPI 2014
CountryBelgium
CityGhent
Period14/5/1114/5/14

Fingerprint

Millimeter waves
Electric lines
Microstrip lines
Foundries
Metals

ASJC Scopus subject areas

  • Signal Processing

Cite this

Amakawa, S., Orii, A., Katayama, K., Takano, K., Motoyoshi, M., Yoshida, T., & Fujishima, M. (2014). Design of well-behaved low-loss millimetre-wave CMOS transmission lines. In 2014 18th IEEE Workshop on Signal and Power Integrity, SPI 2014 - Proceedings [6844526] IEEE Computer Society. https://doi.org/10.1109/SaPIW.2014.6844526

Design of well-behaved low-loss millimetre-wave CMOS transmission lines. / Amakawa, S.; Orii, A.; Katayama, Kosuke; Takano, K.; Motoyoshi, M.; Yoshida, T.; Fujishima, M.

2014 18th IEEE Workshop on Signal and Power Integrity, SPI 2014 - Proceedings. IEEE Computer Society, 2014. 6844526.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Amakawa, S, Orii, A, Katayama, K, Takano, K, Motoyoshi, M, Yoshida, T & Fujishima, M 2014, Design of well-behaved low-loss millimetre-wave CMOS transmission lines. in 2014 18th IEEE Workshop on Signal and Power Integrity, SPI 2014 - Proceedings., 6844526, IEEE Computer Society, 18th IEEE Workshop on Signal and Power Integrity, SPI 2014, Ghent, Belgium, 14/5/11. https://doi.org/10.1109/SaPIW.2014.6844526
Amakawa S, Orii A, Katayama K, Takano K, Motoyoshi M, Yoshida T et al. Design of well-behaved low-loss millimetre-wave CMOS transmission lines. In 2014 18th IEEE Workshop on Signal and Power Integrity, SPI 2014 - Proceedings. IEEE Computer Society. 2014. 6844526 https://doi.org/10.1109/SaPIW.2014.6844526
Amakawa, S. ; Orii, A. ; Katayama, Kosuke ; Takano, K. ; Motoyoshi, M. ; Yoshida, T. ; Fujishima, M. / Design of well-behaved low-loss millimetre-wave CMOS transmission lines. 2014 18th IEEE Workshop on Signal and Power Integrity, SPI 2014 - Proceedings. IEEE Computer Society, 2014.
@inproceedings{e772717ea3db4b7189c3199a2108af6d,
title = "Design of well-behaved low-loss millimetre-wave CMOS transmission lines",
abstract = "It is a challenge to design single-mode transmission lines for above 100 GHz following strict design rules of modern CMOS processes. This paper reports characteristics of three types of microstrip lines in 65 nm CMOS up to 325 GHz, designed with or without using an auto-dummy exclusion layer. The lowest-loss design among the three is a shielded microstrip protected with an exclusion layer. The metal density requirement is met, as is commonly done, by placing sidewalls as far from the signal line as allowed by the design rules. The other two designs are microstrips without sidewalls or the exclusion layer. One of them has high-density auto dummy fill inserted by the foundry and shows significantly higher attenuation than the shielded microstrip. The other is filled with low-density fill that prevents auto dummy fill from being inserted. It is only marginally lossier than the shielded microstrip. The microstrips without sidewalls are found to exhibit more well-behaved attenuation especially above 100 GHz. The frequency dependence of the attenuation of the shielded microstrip, on the other hand, exhibits ripples, indicating possible presence of spurious modes. Attenuation constants estimated by multiline TRL (thru-reflect-line) from lines of various lengths indicate that the longest line measured should be very long, perhaps 2mm or longer, for the estimates to be reliable.",
author = "S. Amakawa and A. Orii and Kosuke Katayama and K. Takano and M. Motoyoshi and T. Yoshida and M. Fujishima",
year = "2014",
doi = "10.1109/SaPIW.2014.6844526",
language = "English",
isbn = "9781479935994",
booktitle = "2014 18th IEEE Workshop on Signal and Power Integrity, SPI 2014 - Proceedings",
publisher = "IEEE Computer Society",
address = "United States",

}

TY - GEN

T1 - Design of well-behaved low-loss millimetre-wave CMOS transmission lines

AU - Amakawa, S.

AU - Orii, A.

AU - Katayama, Kosuke

AU - Takano, K.

AU - Motoyoshi, M.

AU - Yoshida, T.

AU - Fujishima, M.

PY - 2014

Y1 - 2014

N2 - It is a challenge to design single-mode transmission lines for above 100 GHz following strict design rules of modern CMOS processes. This paper reports characteristics of three types of microstrip lines in 65 nm CMOS up to 325 GHz, designed with or without using an auto-dummy exclusion layer. The lowest-loss design among the three is a shielded microstrip protected with an exclusion layer. The metal density requirement is met, as is commonly done, by placing sidewalls as far from the signal line as allowed by the design rules. The other two designs are microstrips without sidewalls or the exclusion layer. One of them has high-density auto dummy fill inserted by the foundry and shows significantly higher attenuation than the shielded microstrip. The other is filled with low-density fill that prevents auto dummy fill from being inserted. It is only marginally lossier than the shielded microstrip. The microstrips without sidewalls are found to exhibit more well-behaved attenuation especially above 100 GHz. The frequency dependence of the attenuation of the shielded microstrip, on the other hand, exhibits ripples, indicating possible presence of spurious modes. Attenuation constants estimated by multiline TRL (thru-reflect-line) from lines of various lengths indicate that the longest line measured should be very long, perhaps 2mm or longer, for the estimates to be reliable.

AB - It is a challenge to design single-mode transmission lines for above 100 GHz following strict design rules of modern CMOS processes. This paper reports characteristics of three types of microstrip lines in 65 nm CMOS up to 325 GHz, designed with or without using an auto-dummy exclusion layer. The lowest-loss design among the three is a shielded microstrip protected with an exclusion layer. The metal density requirement is met, as is commonly done, by placing sidewalls as far from the signal line as allowed by the design rules. The other two designs are microstrips without sidewalls or the exclusion layer. One of them has high-density auto dummy fill inserted by the foundry and shows significantly higher attenuation than the shielded microstrip. The other is filled with low-density fill that prevents auto dummy fill from being inserted. It is only marginally lossier than the shielded microstrip. The microstrips without sidewalls are found to exhibit more well-behaved attenuation especially above 100 GHz. The frequency dependence of the attenuation of the shielded microstrip, on the other hand, exhibits ripples, indicating possible presence of spurious modes. Attenuation constants estimated by multiline TRL (thru-reflect-line) from lines of various lengths indicate that the longest line measured should be very long, perhaps 2mm or longer, for the estimates to be reliable.

UR - http://www.scopus.com/inward/record.url?scp=84904512282&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84904512282&partnerID=8YFLogxK

U2 - 10.1109/SaPIW.2014.6844526

DO - 10.1109/SaPIW.2014.6844526

M3 - Conference contribution

SN - 9781479935994

BT - 2014 18th IEEE Workshop on Signal and Power Integrity, SPI 2014 - Proceedings

PB - IEEE Computer Society

ER -