Design of well-behaved low-loss millimetre-wave CMOS transmission lines

S. Amakawa, A. Orii, K. Katayama, K. Takano, M. Motoyoshi, T. Yoshida, M. Fujishima

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Abstract

It is a challenge to design single-mode transmission lines for above 100 GHz following strict design rules of modern CMOS processes. This paper reports characteristics of three types of microstrip lines in 65 nm CMOS up to 325 GHz, designed with or without using an auto-dummy exclusion layer. The lowest-loss design among the three is a shielded microstrip protected with an exclusion layer. The metal density requirement is met, as is commonly done, by placing sidewalls as far from the signal line as allowed by the design rules. The other two designs are microstrips without sidewalls or the exclusion layer. One of them has high-density auto dummy fill inserted by the foundry and shows significantly higher attenuation than the shielded microstrip. The other is filled with low-density fill that prevents auto dummy fill from being inserted. It is only marginally lossier than the shielded microstrip. The microstrips without sidewalls are found to exhibit more well-behaved attenuation especially above 100 GHz. The frequency dependence of the attenuation of the shielded microstrip, on the other hand, exhibits ripples, indicating possible presence of spurious modes. Attenuation constants estimated by multiline TRL (thru-reflect-line) from lines of various lengths indicate that the longest line measured should be very long, perhaps 2mm or longer, for the estimates to be reliable.

Original languageEnglish
Title of host publication2014 18th IEEE Workshop on Signal and Power Integrity, SPI 2014 - Proceedings
PublisherIEEE Computer Society
ISBN (Print)9781479935994
DOIs
Publication statusPublished - 2014 Jan 1
Event18th IEEE Workshop on Signal and Power Integrity, SPI 2014 - Ghent, Belgium
Duration: 2014 May 112014 May 14

Publication series

Name2014 18th IEEE Workshop on Signal and Power Integrity, SPI 2014 - Proceedings

Other

Other18th IEEE Workshop on Signal and Power Integrity, SPI 2014
CountryBelgium
CityGhent
Period14/5/1114/5/14

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ASJC Scopus subject areas

  • Signal Processing

Cite this

Amakawa, S., Orii, A., Katayama, K., Takano, K., Motoyoshi, M., Yoshida, T., & Fujishima, M. (2014). Design of well-behaved low-loss millimetre-wave CMOS transmission lines. In 2014 18th IEEE Workshop on Signal and Power Integrity, SPI 2014 - Proceedings [6844526] (2014 18th IEEE Workshop on Signal and Power Integrity, SPI 2014 - Proceedings). IEEE Computer Society. https://doi.org/10.1109/SaPIW.2014.6844526