Design optimization of copper patterns and location of power semiconductors and terminals

Yusuke Abe, Akira Hirao, Ryoichi Kato, Yoshinari Ikeda, Victor Parque, Muhammad Khairi Faiz, Makoto Yoshida, Tomoyuki Miyashita

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In recent years, SiC power modules have attracted a lot of attention because they offer higher frequency and density as compared to the conventional Si power module. However high speed switching inevitably lead to the generation of surge voltage which may damage the power module. The design of layout, which composed of copper patterns, power semiconductors and terminals, is one of the factors that is necessary to overcome the problem. In this paper, the layout design of the half-bridge power module is optimized to reduce its internal inductance. The inductance was evaluated by electromagnetic field simulation.

Original languageEnglish
Title of host publication2021 International Conference on Electronics Packaging, ICEP 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages157-158
Number of pages2
ISBN (Electronic)9784991191114
DOIs
Publication statusPublished - 2021 May 12
Event20th International Conference on Electronics Packaging, ICEP 2021 - Tokyo, Japan
Duration: 2021 May 122021 May 14

Publication series

Name2021 International Conference on Electronics Packaging, ICEP 2021

Conference

Conference20th International Conference on Electronics Packaging, ICEP 2021
Country/TerritoryJapan
CityTokyo
Period21/5/1221/5/14

Keywords

  • Inductance
  • Layout optimization
  • Power module

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Mechanics of Materials
  • Electronic, Optical and Magnetic Materials
  • Instrumentation

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