Design system for special purpose processor executing algorithms described by higher level language

K. Shirai, Takeshi Ikenaga, H. Kitabatake

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

In order to satisfy the user's requirements which are described by a high level language, a large number of possibilities must be examined to find a good design. The case in which the architecture is restricted to that having a usual instruction set is considered. The main objective of the system is to generate a minimal set of hardware which can execute the given algorithms and also satisfy other requirements such as speed, hardware cost, and I/O condition. It realizes an integrated system which provides not only a hardware design environment but also a software one by generating automatically a higher-level language compiler which has optimization capability for the processor at the same time. As a practical example, the design of a special-purpose processor which can execute thirteen typical digital signal processing algorithms is demonstrated. It is shown that the design system can provide ASIC users a total environment to design and use special-purpose processors. The software development tools are superior to those usable for general-purpose DSPs.

Original languageEnglish
Title of host publicationProceedings of the Third Annual IEEE ASIC Seminar and Exhibit
Place of PublicationPiscataway, NJ, United States
PublisherPubl by IEEE
Publication statusPublished - 1990
EventProceedings of the 3rd Annual IEEE ASIC Seminar and Exhibit - Rochester, NY, USA
Duration: 1990 Sep 171990 Sep 21

Other

OtherProceedings of the 3rd Annual IEEE ASIC Seminar and Exhibit
CityRochester, NY, USA
Period90/9/1790/9/21

Fingerprint

High level languages
Hardware
Application specific integrated circuits
Digital signal processing
Software engineering
Costs

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Shirai, K., Ikenaga, T., & Kitabatake, H. (1990). Design system for special purpose processor executing algorithms described by higher level language. In Proceedings of the Third Annual IEEE ASIC Seminar and Exhibit Piscataway, NJ, United States: Publ by IEEE.

Design system for special purpose processor executing algorithms described by higher level language. / Shirai, K.; Ikenaga, Takeshi; Kitabatake, H.

Proceedings of the Third Annual IEEE ASIC Seminar and Exhibit. Piscataway, NJ, United States : Publ by IEEE, 1990.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Shirai, K, Ikenaga, T & Kitabatake, H 1990, Design system for special purpose processor executing algorithms described by higher level language. in Proceedings of the Third Annual IEEE ASIC Seminar and Exhibit. Publ by IEEE, Piscataway, NJ, United States, Proceedings of the 3rd Annual IEEE ASIC Seminar and Exhibit, Rochester, NY, USA, 90/9/17.
Shirai K, Ikenaga T, Kitabatake H. Design system for special purpose processor executing algorithms described by higher level language. In Proceedings of the Third Annual IEEE ASIC Seminar and Exhibit. Piscataway, NJ, United States: Publ by IEEE. 1990
Shirai, K. ; Ikenaga, Takeshi ; Kitabatake, H. / Design system for special purpose processor executing algorithms described by higher level language. Proceedings of the Third Annual IEEE ASIC Seminar and Exhibit. Piscataway, NJ, United States : Publ by IEEE, 1990.
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