Determination of interconnect structural parameters for best- and worst-case delays

Atsushi Kurokawa, Hiroo Masuda, Junko Fuji, Toshinori Inoshita, Akira Kasebe, Zhangcai Huang, Yasuaki Inoue

    Research output: Contribution to journalArticle

    3 Citations (Scopus)

    Abstract

    In general, a corner model with best- and worst-case delay conditions is used in static timing analysis (STA). The best- and worst-case delays of a stage are defined as the fastest and slowest delays from a cell input to the next cell input. In this paper, we present a methodology for determining the parameters that yield the best- and worst-case delays when interconnect structural parameters have the minimum and maximum values with process variations. We also present analysis results of our circuit model using the methodology. The min and max conditions for the time constant are found to be (+Δw, + Δt, + Δh) & (-Δw, - Δt, -Δh), respectively. Here, +Δ or -Δ means the max or min comer value of each parameter variation, where w is the width, t is the interconnect thickness, and h is the height. Best and worst conditions for delay time are as follows: 1) given a circuit with an optimum driver, dense interconnects, and small branch capacitance, the best and worst conditions are respectively (-Δw, +Δt. +Δh) & (+Δw, +Δt, -Δh), 2) given driver and/or via resistances that are higher than the interconnect resistance, dense interconnects, and small branch capacitance, they are (-Δw, -Δt, +Δh) & (+Δw, +Δt, -Δh), and 3) for other conditions, they are (+Δw, +Δt, -+Δh) & (-Δw, -Δt, -Δh). Moreover, if there must be only one condition each for the best- and worst-case delays, they are (+Δw, +Δt, +Δh) & (-Δw, -Δt, -Δh).

    Original languageEnglish
    Pages (from-to)856-864
    Number of pages9
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE89-A
    Issue number4
    DOIs
    Publication statusPublished - 2006 Apr

    Fingerprint

    Structural Parameters
    Interconnect
    Capacitance
    Networks (circuits)
    Time delay
    Driver
    Branch
    Timing Analysis
    Process Variation
    Methodology
    Cell
    Delay Time
    Static Analysis
    Time Constant
    Model

    Keywords

    • Capacitance extraction
    • Interconnect
    • Process variation
    • Static timing analysis
    • Worst-case delay

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Hardware and Architecture
    • Information Systems

    Cite this

    Determination of interconnect structural parameters for best- and worst-case delays. / Kurokawa, Atsushi; Masuda, Hiroo; Fuji, Junko; Inoshita, Toshinori; Kasebe, Akira; Huang, Zhangcai; Inoue, Yasuaki.

    In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E89-A, No. 4, 04.2006, p. 856-864.

    Research output: Contribution to journalArticle

    Kurokawa, Atsushi ; Masuda, Hiroo ; Fuji, Junko ; Inoshita, Toshinori ; Kasebe, Akira ; Huang, Zhangcai ; Inoue, Yasuaki. / Determination of interconnect structural parameters for best- and worst-case delays. In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 2006 ; Vol. E89-A, No. 4. pp. 856-864.
    @article{8ef56460462440dfa612f81a1c9cb2ea,
    title = "Determination of interconnect structural parameters for best- and worst-case delays",
    abstract = "In general, a corner model with best- and worst-case delay conditions is used in static timing analysis (STA). The best- and worst-case delays of a stage are defined as the fastest and slowest delays from a cell input to the next cell input. In this paper, we present a methodology for determining the parameters that yield the best- and worst-case delays when interconnect structural parameters have the minimum and maximum values with process variations. We also present analysis results of our circuit model using the methodology. The min and max conditions for the time constant are found to be (+Δw, + Δt, + Δh) & (-Δw, - Δt, -Δh), respectively. Here, +Δ or -Δ means the max or min comer value of each parameter variation, where w is the width, t is the interconnect thickness, and h is the height. Best and worst conditions for delay time are as follows: 1) given a circuit with an optimum driver, dense interconnects, and small branch capacitance, the best and worst conditions are respectively (-Δw, +Δt. +Δh) & (+Δw, +Δt, -Δh), 2) given driver and/or via resistances that are higher than the interconnect resistance, dense interconnects, and small branch capacitance, they are (-Δw, -Δt, +Δh) & (+Δw, +Δt, -Δh), and 3) for other conditions, they are (+Δw, +Δt, -+Δh) & (-Δw, -Δt, -Δh). Moreover, if there must be only one condition each for the best- and worst-case delays, they are (+Δw, +Δt, +Δh) & (-Δw, -Δt, -Δh).",
    keywords = "Capacitance extraction, Interconnect, Process variation, Static timing analysis, Worst-case delay",
    author = "Atsushi Kurokawa and Hiroo Masuda and Junko Fuji and Toshinori Inoshita and Akira Kasebe and Zhangcai Huang and Yasuaki Inoue",
    year = "2006",
    month = "4",
    doi = "10.1093/ietfec/e89-a.4.856",
    language = "English",
    volume = "E89-A",
    pages = "856--864",
    journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
    issn = "0916-8508",
    publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
    number = "4",

    }

    TY - JOUR

    T1 - Determination of interconnect structural parameters for best- and worst-case delays

    AU - Kurokawa, Atsushi

    AU - Masuda, Hiroo

    AU - Fuji, Junko

    AU - Inoshita, Toshinori

    AU - Kasebe, Akira

    AU - Huang, Zhangcai

    AU - Inoue, Yasuaki

    PY - 2006/4

    Y1 - 2006/4

    N2 - In general, a corner model with best- and worst-case delay conditions is used in static timing analysis (STA). The best- and worst-case delays of a stage are defined as the fastest and slowest delays from a cell input to the next cell input. In this paper, we present a methodology for determining the parameters that yield the best- and worst-case delays when interconnect structural parameters have the minimum and maximum values with process variations. We also present analysis results of our circuit model using the methodology. The min and max conditions for the time constant are found to be (+Δw, + Δt, + Δh) & (-Δw, - Δt, -Δh), respectively. Here, +Δ or -Δ means the max or min comer value of each parameter variation, where w is the width, t is the interconnect thickness, and h is the height. Best and worst conditions for delay time are as follows: 1) given a circuit with an optimum driver, dense interconnects, and small branch capacitance, the best and worst conditions are respectively (-Δw, +Δt. +Δh) & (+Δw, +Δt, -Δh), 2) given driver and/or via resistances that are higher than the interconnect resistance, dense interconnects, and small branch capacitance, they are (-Δw, -Δt, +Δh) & (+Δw, +Δt, -Δh), and 3) for other conditions, they are (+Δw, +Δt, -+Δh) & (-Δw, -Δt, -Δh). Moreover, if there must be only one condition each for the best- and worst-case delays, they are (+Δw, +Δt, +Δh) & (-Δw, -Δt, -Δh).

    AB - In general, a corner model with best- and worst-case delay conditions is used in static timing analysis (STA). The best- and worst-case delays of a stage are defined as the fastest and slowest delays from a cell input to the next cell input. In this paper, we present a methodology for determining the parameters that yield the best- and worst-case delays when interconnect structural parameters have the minimum and maximum values with process variations. We also present analysis results of our circuit model using the methodology. The min and max conditions for the time constant are found to be (+Δw, + Δt, + Δh) & (-Δw, - Δt, -Δh), respectively. Here, +Δ or -Δ means the max or min comer value of each parameter variation, where w is the width, t is the interconnect thickness, and h is the height. Best and worst conditions for delay time are as follows: 1) given a circuit with an optimum driver, dense interconnects, and small branch capacitance, the best and worst conditions are respectively (-Δw, +Δt. +Δh) & (+Δw, +Δt, -Δh), 2) given driver and/or via resistances that are higher than the interconnect resistance, dense interconnects, and small branch capacitance, they are (-Δw, -Δt, +Δh) & (+Δw, +Δt, -Δh), and 3) for other conditions, they are (+Δw, +Δt, -+Δh) & (-Δw, -Δt, -Δh). Moreover, if there must be only one condition each for the best- and worst-case delays, they are (+Δw, +Δt, +Δh) & (-Δw, -Δt, -Δh).

    KW - Capacitance extraction

    KW - Interconnect

    KW - Process variation

    KW - Static timing analysis

    KW - Worst-case delay

    UR - http://www.scopus.com/inward/record.url?scp=33646260674&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=33646260674&partnerID=8YFLogxK

    U2 - 10.1093/ietfec/e89-a.4.856

    DO - 10.1093/ietfec/e89-a.4.856

    M3 - Article

    AN - SCOPUS:33646260674

    VL - E89-A

    SP - 856

    EP - 864

    JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    SN - 0916-8508

    IS - 4

    ER -