Deterministic inter-core synchronization with periodically all-in-phase clocking for low-power multi-core SoCs

Koichi Nose, Atsufumi Shibayama, Hiroshi Kodama, Masayuki Mizuno, Masato Edahiro, Naoki Nishi

Research output: Contribution to journalConference article

Abstract

Periodically all-in-phase clocking (8-step frequency increments with a 4.5ns switching time) and deterministic synchronous bus wrappers (synchronized data transfer among different frequency cores) are developed for dynamic voltage- and frequency-scaling multi-core SoCs. A maximum of 60% power reduction in MPEG-4 decoding with 1.5 to 2X throughput increase are confirmed.

Original languageEnglish
Article number16.3
Pages (from-to)238-239+618
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume48
Publication statusPublished - 2005
Externally publishedYes
Event2005 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States
Duration: 2005 Feb 62005 Feb 10

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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