Takao Kaneko, Hironori Yamauchi, Atsushi Iwata, Yasuyuki Matsuya

Research output: Contribution to journalArticle


A high-speed programmable digital speech signal processor VLSI (DSSPI) with an 18-bit floating-point architecture and 32-bit micro-instructions is developed using 1. 2 mu m CMOS technology. This chip integrates a normalizing floating-point ALU, a 512w dual-port data RAM, and a 4Kw micro-program ROM to enable normalizing floating-point operations within a 50nsec machine-cycle. A high-speed communication interface that allows a wide variety of configurations to suit various user requirements is provided. The processor VLSI is designed almost entirely with a top-down DA system, which significantly reduces chip size and design time.

Original languageEnglish
Pages (from-to)305-311
Number of pages7
JournalDenki Tsushin Kenkyujo kenkyu jitsuyoka hokoku
Issue number4-5
Publication statusPublished - 1988 Jan 1
Externally publishedYes

ASJC Scopus subject areas

  • Engineering(all)

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    Kaneko, T., Yamauchi, H., Iwata, A., & Matsuya, Y. (1988). DIGITAL SPEECH SIGNAL PROCESSOR VLSI: DSSP1. Denki Tsushin Kenkyujo kenkyu jitsuyoka hokoku, 37(4-5), 305-311.