A high-speed programmable digital speech signal processor VLSI (DSSPI) with an 18-bit floating-point architecture and 32-bit micro-instructions is developed using 1. 2 mu m CMOS technology. This chip integrates a normalizing floating-point ALU, a 512w dual-port data RAM, and a 4Kw micro-program ROM to enable normalizing floating-point operations within a 50nsec machine-cycle. A high-speed communication interface that allows a wide variety of configurations to suit various user requirements is provided. The processor VLSI is designed almost entirely with a top-down DA system, which significantly reduces chip size and design time.
|Number of pages||7|
|Journal||Denki Tsushin Kenkyujo kenkyu jitsuyoka hokoku|
|Publication status||Published - 1988 Jan 1|
ASJC Scopus subject areas