DIGITAL SPEECH SIGNAL PROCESSOR VLSI

DSSP1.

Takao Kaneko, Hironori Yamauchi, Atsushi Iwata, Yasuyuki Matsuya

Research output: Contribution to journalArticle

Abstract

A high-speed programmable digital speech signal processor VLSI (DSSPI) with an 18-bit floating-point architecture and 32-bit micro-instructions is developed using 1. 2 mu m CMOS technology. This chip integrates a normalizing floating-point ALU, a 512w dual-port data RAM, and a 4Kw micro-program ROM to enable normalizing floating-point operations within a 50nsec machine-cycle. A high-speed communication interface that allows a wide variety of configurations to suit various user requirements is provided. The processor VLSI is designed almost entirely with a top-down DA system, which significantly reduces chip size and design time.

Original languageEnglish
Pages (from-to)305-311
Number of pages7
JournalDenki Tsushin Kenkyujo kenkyu jitsuyoka hokoku
Volume37
Issue number4-5
Publication statusPublished - 1988
Externally publishedYes

Fingerprint

ROM
Random access storage
Communication

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Kaneko, T., Yamauchi, H., Iwata, A., & Matsuya, Y. (1988). DIGITAL SPEECH SIGNAL PROCESSOR VLSI: DSSP1. Denki Tsushin Kenkyujo kenkyu jitsuyoka hokoku, 37(4-5), 305-311.

DIGITAL SPEECH SIGNAL PROCESSOR VLSI : DSSP1. / Kaneko, Takao; Yamauchi, Hironori; Iwata, Atsushi; Matsuya, Yasuyuki.

In: Denki Tsushin Kenkyujo kenkyu jitsuyoka hokoku, Vol. 37, No. 4-5, 1988, p. 305-311.

Research output: Contribution to journalArticle

Kaneko, T, Yamauchi, H, Iwata, A & Matsuya, Y 1988, 'DIGITAL SPEECH SIGNAL PROCESSOR VLSI: DSSP1.', Denki Tsushin Kenkyujo kenkyu jitsuyoka hokoku, vol. 37, no. 4-5, pp. 305-311.
Kaneko, Takao ; Yamauchi, Hironori ; Iwata, Atsushi ; Matsuya, Yasuyuki. / DIGITAL SPEECH SIGNAL PROCESSOR VLSI : DSSP1. In: Denki Tsushin Kenkyujo kenkyu jitsuyoka hokoku. 1988 ; Vol. 37, No. 4-5. pp. 305-311.
@article{73d487c7654f451a96ee193c51065133,
title = "DIGITAL SPEECH SIGNAL PROCESSOR VLSI: DSSP1.",
abstract = "A high-speed programmable digital speech signal processor VLSI (DSSPI) with an 18-bit floating-point architecture and 32-bit micro-instructions is developed using 1. 2 mu m CMOS technology. This chip integrates a normalizing floating-point ALU, a 512w dual-port data RAM, and a 4Kw micro-program ROM to enable normalizing floating-point operations within a 50nsec machine-cycle. A high-speed communication interface that allows a wide variety of configurations to suit various user requirements is provided. The processor VLSI is designed almost entirely with a top-down DA system, which significantly reduces chip size and design time.",
author = "Takao Kaneko and Hironori Yamauchi and Atsushi Iwata and Yasuyuki Matsuya",
year = "1988",
language = "English",
volume = "37",
pages = "305--311",
journal = "Denki Tsushin Kenkyujo kenkyu jitsuyoka hokoku",
issn = "0415-3200",
number = "4-5",

}

TY - JOUR

T1 - DIGITAL SPEECH SIGNAL PROCESSOR VLSI

T2 - DSSP1.

AU - Kaneko, Takao

AU - Yamauchi, Hironori

AU - Iwata, Atsushi

AU - Matsuya, Yasuyuki

PY - 1988

Y1 - 1988

N2 - A high-speed programmable digital speech signal processor VLSI (DSSPI) with an 18-bit floating-point architecture and 32-bit micro-instructions is developed using 1. 2 mu m CMOS technology. This chip integrates a normalizing floating-point ALU, a 512w dual-port data RAM, and a 4Kw micro-program ROM to enable normalizing floating-point operations within a 50nsec machine-cycle. A high-speed communication interface that allows a wide variety of configurations to suit various user requirements is provided. The processor VLSI is designed almost entirely with a top-down DA system, which significantly reduces chip size and design time.

AB - A high-speed programmable digital speech signal processor VLSI (DSSPI) with an 18-bit floating-point architecture and 32-bit micro-instructions is developed using 1. 2 mu m CMOS technology. This chip integrates a normalizing floating-point ALU, a 512w dual-port data RAM, and a 4Kw micro-program ROM to enable normalizing floating-point operations within a 50nsec machine-cycle. A high-speed communication interface that allows a wide variety of configurations to suit various user requirements is provided. The processor VLSI is designed almost entirely with a top-down DA system, which significantly reduces chip size and design time.

UR - http://www.scopus.com/inward/record.url?scp=0023827201&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0023827201&partnerID=8YFLogxK

M3 - Article

VL - 37

SP - 305

EP - 311

JO - Denki Tsushin Kenkyujo kenkyu jitsuyoka hokoku

JF - Denki Tsushin Kenkyujo kenkyu jitsuyoka hokoku

SN - 0415-3200

IS - 4-5

ER -