Distributed BIST technique and its test design platform for VLSIs

Takeshi Ikenaga, Takeshi Ogura

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

This paper proposes a distributed built-in self-test (BIST) technique and its test design platform for VLSIs. This BIST has lower hardware overhead pattern generators, compressors and a controller. The platform cuts down on the number of complicated operations needed for the BIST insertion and evaluation, so the BIST implementation turn-around-time (TAT) is dramatically reduced. Experimental results for the 110k-gate arithmetic execution blocks of an image-processing LSI show that using this BIST structure and platform enables the entire BIST implementation within five days. The implemented BIST has a 1% hardware overhead and 96% fault coverage. This platform will significantly reduce testing costs for time-to-market and mass-produced LSIs.

Original languageEnglish
Pages (from-to)1618-1623
Number of pages6
JournalIEICE Transactions on Electronics
VolumeE78-C
Issue number11
Publication statusPublished - 1995 Nov
Externally publishedYes

Fingerprint

Built-in self test
Hardware
Turnaround time
Compressors
Image processing
Controllers
Testing
Costs

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Distributed BIST technique and its test design platform for VLSIs. / Ikenaga, Takeshi; Ogura, Takeshi.

In: IEICE Transactions on Electronics, Vol. E78-C, No. 11, 11.1995, p. 1618-1623.

Research output: Contribution to journalArticle

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