DIVIDED WORD-LINE STRUCTURE IN THE STATIC RAM AND ITS APPLICATION TO A 64K FULL CMOS RAM.

Masahiko Yoshimoto, Kenji Anami, Hirofumi Shinohara, Tsutomu Yoshihara, Hiroshi Takagi, Shigeo Nagao, Shinpei Kayano, Takao Nakano

Research output: Contribution to journalArticle

135 Citations (Scopus)

Abstract

A divided word-line (DWL) structure which solves inherent problems encountered in VLSI static RAM's is described. The key feature is to divide the word-line and to select it hierarchically with little area penalty using conventional process technology. In the application of the DWL structure, an 8K multiplied by 8 full CMOS RAM has been developed with 2 mu m double polysilicon technology. The RAM has a typical access time of 60 ns. An operating current of 20 ma was obtained with a simple static design. The six transistor cell configuration achieved a low standby current of less than 10 na. For further improvement in the speed performance, second poly-Si layer was replaced with a polycide (poly-Si plus MoSi2) layer, thus offering a 50 ns address access time.

Original languageEnglish
Pages (from-to)479-485
Number of pages7
JournalIEEE Journal of Solid-State Circuits
VolumeSC-18
Issue number5
Publication statusPublished - 1983 Oct
Externally publishedYes

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Random access storage
Polysilicon
Transistors

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Yoshimoto, M., Anami, K., Shinohara, H., Yoshihara, T., Takagi, H., Nagao, S., ... Nakano, T. (1983). DIVIDED WORD-LINE STRUCTURE IN THE STATIC RAM AND ITS APPLICATION TO A 64K FULL CMOS RAM. IEEE Journal of Solid-State Circuits, SC-18(5), 479-485.

DIVIDED WORD-LINE STRUCTURE IN THE STATIC RAM AND ITS APPLICATION TO A 64K FULL CMOS RAM. / Yoshimoto, Masahiko; Anami, Kenji; Shinohara, Hirofumi; Yoshihara, Tsutomu; Takagi, Hiroshi; Nagao, Shigeo; Kayano, Shinpei; Nakano, Takao.

In: IEEE Journal of Solid-State Circuits, Vol. SC-18, No. 5, 10.1983, p. 479-485.

Research output: Contribution to journalArticle

Yoshimoto, M, Anami, K, Shinohara, H, Yoshihara, T, Takagi, H, Nagao, S, Kayano, S & Nakano, T 1983, 'DIVIDED WORD-LINE STRUCTURE IN THE STATIC RAM AND ITS APPLICATION TO A 64K FULL CMOS RAM.', IEEE Journal of Solid-State Circuits, vol. SC-18, no. 5, pp. 479-485.
Yoshimoto, Masahiko ; Anami, Kenji ; Shinohara, Hirofumi ; Yoshihara, Tsutomu ; Takagi, Hiroshi ; Nagao, Shigeo ; Kayano, Shinpei ; Nakano, Takao. / DIVIDED WORD-LINE STRUCTURE IN THE STATIC RAM AND ITS APPLICATION TO A 64K FULL CMOS RAM. In: IEEE Journal of Solid-State Circuits. 1983 ; Vol. SC-18, No. 5. pp. 479-485.
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