Dopant profile engineering of CMOS devices formed by non-melt laser spike annealing

Akio Shima; Yun Wang; Deepak Upadhyaya; Lucia Feng; Somit Talwar; Atsushi Hiraiwa

doi:10.1109/.2005.1469246

Dopant profile engineering of CMOS devices formed by non-melt laser spike annealing

Akio Shima^*, Yun Wang, Deepak Upadhyaya, Lucia Feng, Somit Talwar, Atsushi Hiraiwa

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

24 Citations (Scopus)

Abstract

We optimized the halo profile and deep source/drain junction profile of the devices that were fabricated by non-melt laser spike annealing (LSA). The optimized devices achieved 10%- and 20%-better performance compared to those by the conventional LSA and rapid thermal annealing (RTA), respectively. The hot carrier degradation was also reduced to an RTA-comparable level by the halo optimization. From these results we concluded that the dopant profile engineering specific to LSA is a key to obtaining good device performance and that the devices by the optimized LSA process are the most promising for hp65-node and beyond.

Original language	English
Title of host publication	Digest of Technical Papers - Symposium on VLSI Technology
Pages	144-145
Number of pages	2
Volume	2005
DOIs	https://doi.org/10.1109/.2005.1469246
Publication status	Published - 2005
Externally published	Yes
Event	2005 Symposium on VLSI Technology - Kyoto, Japan Duration: 2005 Jun 14 → 2005 Jun 14

Other

Other	2005 Symposium on VLSI Technology
Country/Territory	Japan
City	Kyoto
Period	05/6/14 → 05/6/14

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/.2005.1469246

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title = "Dopant profile engineering of CMOS devices formed by non-melt laser spike annealing",

abstract = "We optimized the halo profile and deep source/drain junction profile of the devices that were fabricated by non-melt laser spike annealing (LSA). The optimized devices achieved 10%- and 20%-better performance compared to those by the conventional LSA and rapid thermal annealing (RTA), respectively. The hot carrier degradation was also reduced to an RTA-comparable level by the halo optimization. From these results we concluded that the dopant profile engineering specific to LSA is a key to obtaining good device performance and that the devices by the optimized LSA process are the most promising for hp65-node and beyond.",

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AU - Shima, Akio

AU - Wang, Yun

AU - Upadhyaya, Deepak

AU - Feng, Lucia

AU - Talwar, Somit

AU - Hiraiwa, Atsushi

PY - 2005

Y1 - 2005

N2 - We optimized the halo profile and deep source/drain junction profile of the devices that were fabricated by non-melt laser spike annealing (LSA). The optimized devices achieved 10%- and 20%-better performance compared to those by the conventional LSA and rapid thermal annealing (RTA), respectively. The hot carrier degradation was also reduced to an RTA-comparable level by the halo optimization. From these results we concluded that the dopant profile engineering specific to LSA is a key to obtaining good device performance and that the devices by the optimized LSA process are the most promising for hp65-node and beyond.

AB - We optimized the halo profile and deep source/drain junction profile of the devices that were fabricated by non-melt laser spike annealing (LSA). The optimized devices achieved 10%- and 20%-better performance compared to those by the conventional LSA and rapid thermal annealing (RTA), respectively. The hot carrier degradation was also reduced to an RTA-comparable level by the halo optimization. From these results we concluded that the dopant profile engineering specific to LSA is a key to obtaining good device performance and that the devices by the optimized LSA process are the most promising for hp65-node and beyond.

UR - http://www.scopus.com/inward/record.url?scp=33745170708&partnerID=8YFLogxK

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DO - 10.1109/.2005.1469246

M3 - Conference contribution

AN - SCOPUS:33745170708

VL - 2005

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BT - Digest of Technical Papers - Symposium on VLSI Technology

T2 - 2005 Symposium on VLSI Technology

Y2 - 14 June 2005 through 14 June 2005

ER -

Dopant profile engineering of CMOS devices formed by non-melt laser spike annealing

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