DOUBLE STACKED CAPACITOR WITH SELF-ALIGNED POLY SOURCE/DRAIN TRANSISTOR (DSP) CELL FOR MEGABIT DRAM.

K. Tsukamoto, M. Shimizu, Masahide Inuishi, Y. Matsuda, H. Oda, H. Morita, M. Nakajima, K. Kobayashi, Y. Mashiko, Y. Akasaka

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

A DRAM cell with a double stacked capacitor and a self-aligned poly source/drain transistor (DSP) cell is described. A storage capacitor is composed of two capacitors stacked in a trench. The first polysilicon acts as a storage node; it is also used as a self-aligned poly source/drain of the access transistor. The isolation region is formed by refilled oxide in openings between the active areas of the first polysilicon. This unique self-aligned structure results in a cell size of 5. 95 mu m**2.

Original languageEnglish
Pages (from-to)328-331
Number of pages4
JournalUnknown Journal
Publication statusPublished - 1987
Externally publishedYes

Fingerprint

Dynamic random access storage
Polysilicon
capacitors
Transistors
Capacitors
transistors
Capacitor storage
cells
Oxides
isolation
oxides

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Tsukamoto, K., Shimizu, M., Inuishi, M., Matsuda, Y., Oda, H., Morita, H., ... Akasaka, Y. (1987). DOUBLE STACKED CAPACITOR WITH SELF-ALIGNED POLY SOURCE/DRAIN TRANSISTOR (DSP) CELL FOR MEGABIT DRAM. Unknown Journal, 328-331.

DOUBLE STACKED CAPACITOR WITH SELF-ALIGNED POLY SOURCE/DRAIN TRANSISTOR (DSP) CELL FOR MEGABIT DRAM. / Tsukamoto, K.; Shimizu, M.; Inuishi, Masahide; Matsuda, Y.; Oda, H.; Morita, H.; Nakajima, M.; Kobayashi, K.; Mashiko, Y.; Akasaka, Y.

In: Unknown Journal, 1987, p. 328-331.

Research output: Contribution to journalArticle

Tsukamoto, K, Shimizu, M, Inuishi, M, Matsuda, Y, Oda, H, Morita, H, Nakajima, M, Kobayashi, K, Mashiko, Y & Akasaka, Y 1987, 'DOUBLE STACKED CAPACITOR WITH SELF-ALIGNED POLY SOURCE/DRAIN TRANSISTOR (DSP) CELL FOR MEGABIT DRAM.', Unknown Journal, pp. 328-331.
Tsukamoto, K. ; Shimizu, M. ; Inuishi, Masahide ; Matsuda, Y. ; Oda, H. ; Morita, H. ; Nakajima, M. ; Kobayashi, K. ; Mashiko, Y. ; Akasaka, Y. / DOUBLE STACKED CAPACITOR WITH SELF-ALIGNED POLY SOURCE/DRAIN TRANSISTOR (DSP) CELL FOR MEGABIT DRAM. In: Unknown Journal. 1987 ; pp. 328-331.
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AU - Shimizu, M.

AU - Inuishi, Masahide

AU - Matsuda, Y.

AU - Oda, H.

AU - Morita, H.

AU - Nakajima, M.

AU - Kobayashi, K.

AU - Mashiko, Y.

AU - Akasaka, Y.

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