Dummy filling methods for reducing interconnect capacitance and number of fills

Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Chang Wei Fong, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    29 Citations (Scopus)

    Abstract

    In recent system-on-chip (SoC) designs, floating dummy metals inserted for planarization have created serious problems because of increased interconnect capacitance and the enormous amount of fill required. We present new methods to reduce the interconnect capacitance and the amount of dummy metals needed. These techniques include three ways of filling: (1) improved floating square fills, (2) floating parallel lines, and (3) floating perpendicular lines (with spacing between dummy metals above and below signal lines). We also present efficient simple formulas for estimating the appropriate spacing and number of fills. In our experiments, the capacitance increase using the traditional regular square method was 13.1%, while that using the methods of improved square fills, extended parallel lines, and perpendicular lines was 2.5%, 2.4%, and 1.1%, respectively. Moreover, the number of necessary dummy metals can be reduced by two orders of magnitude through use of the parallel line method.

    Original languageEnglish
    Title of host publicationProceedings - International Symposium on Quality Electronic Design, ISQED
    Pages586-591
    Number of pages6
    DOIs
    Publication statusPublished - 2005
    Event6th International Symposium on Quality Electronic Design, ISQED 2005 - San Jose, CA
    Duration: 2005 Mar 212005 Mar 23

    Other

    Other6th International Symposium on Quality Electronic Design, ISQED 2005
    CitySan Jose, CA
    Period05/3/2105/3/23

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering
    • Safety, Risk, Reliability and Quality

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